10vrstvá vysokorychlostní konstrukce desek plošných spojů pro DDR5 a PCIe

A ten-layer board can support demanding digital links, but layer count alone does not establish compliance. The result depends on the complete channel: transmitter package, breakout, vias, routed transmission line, connector or cable interface, receiver package and equalization. A board with premium laminate can still fail because of a resonant via stub or a broken return path; a shorter channel on a more economical material can pass when the transitions are well designed.

This page is organized around channel engineering. It separates public protocol facts from form-factor-specific limits, shows how to allocate loss and discontinuity margin, and defines the evidence a fabricator can provide. Detailed geometry belongs in the impedance-control specification, while layout execution belongs in the průvodce směrováním.

Start with the Channel, Not the Protocol Label

“PCIe Gen6 capable,” “112G material” and “800G PCB” are incomplete descriptions. A protocol can appear in several form factors with different connectors, reaches and channel masks. The same data rate can be routed on a short chip-to-chip link, a motherboard-to-add-in-card link or a backplane with very different loss allocation.

The supplier should not promise support for an interface from material name and layer count alone. A responsible response is conditional: the proposed construction can be quoted and built after the customer’s loss, impedance and transition requirements are matched to a released stackup.

What the Data Rate Does-and Does Not-Tell You

Data rate establishes a starting point for spectral analysis, but modulation matters. PCI Express 5.0 operates at 32 GT/s using NRZ, giving a 16 GHz Nyquist frequency. PCI Express 6.0 operates at 64 GT/s using PAM4 and retains a 16 GHz Nyquist frequency while adding FEC and FLIT operation. PCI Express 7.0 version 1.0 was released in 2025 at 128 GT/s using PAM4, which moves the Nyquist frequency to 32 GHz. These public facts do not by themselves define the board loss budget; the applicable form-factor specification does.

Nyquist frequency is not the highest frequency that matters. Rise time, jitter, equalization and discontinuities create sensitivity above Nyquist. At the same time, using an arbitrarily high frequency for every calculation can over-constrain the board. Use the bandwidth and masks in the applicable compliance method.

Build an Insertion-Loss and Discontinuity Budget

A channel budget should account for every physical section between the compliance reference planes. For example, public PCI-SIG material has shown a 36 dB total channel insertion-loss budget at 16 GHz for a PCIe 5.0 CEM channel. That number belongs to that defined channel and should not be generalized to every 32 GT/s topology. The board designer must subtract the package, connector, add-in-card or baseboard allocations that apply to the implementation before deciding how much trace loss is available.

Loss is not a single dB-per-inch constant

Trace loss changes with frequency, line width, dielectric thickness, copper profile, glass construction and whether the route is microstrip or stripline. A data-sheet Df cannot be converted into a universal reach. Connector and via loss are also frequency-dependent, and a stub resonance can create a narrow deep notch that is more damaging than a smooth average loss.

Return loss and crosstalk consume margin too

A link can meet an insertion-loss number and still fail because impedance discontinuities, mode conversion, near-end or far-end crosstalk, or power-supply noise close the eye. Serial-link assessment should therefore use the protocol’s required metrics-such as channel operating margin, COM, statistical eye or a vendor-specific link model-rather than a trace-loss spreadsheet alone.

Select Material, Copper and Geometry Together

Material selection should be based on the extracted channel, not a protocol table. The dielectric system, copper roughness and stackup geometry work together. A wider line on a thin dielectric may reduce conductor loss but consume routing space; a lower-Dk material can change the width needed for the same impedance; a very smooth foil can reduce loss but require a qualified adhesion process.

Hybrid constructions place a low-loss system around the layers carrying the most sensitive channels while using a qualified conventional material elsewhere. They can be cost-effective, but the exact material pair, bonding layer and press cycle must be released. The materials selection guide explains why MEGTRON, I-Tera, Tachyon and Rogers families cannot be treated as automatic equivalents.

Do not assign protocol generations to laminate names

Statements such as “MEGTRON 6 supports eight inches of PCIe Gen5” or “Tachyon is required for 112G” omit too many variables to be reliable. A short 112G route may close on several low-loss systems; a long route with multiple connectors may require a lower-loss construction or a different system architecture. The correct output is a simulated margin for the actual route and manufacturing model.

Glass weave and skew

At 112G and above, local delay variation from glass weave can become comparable with the intra-pair skew budget. Spread glass, routing angle, trace width and pair placement should be chosen with the actual construction. The board drawing should identify any restricted glass styles or the skew mitigation used by layout.

Via Transitions, Back-Drilling and Breakout

A through via includes pad capacitance, barrel inductance and an unused barrel section below or above the signal connection. That unused section behaves as a stub. Its resonance depends on electrical length and dielectric environment, so a fixed “maximum stub by protocol” table is only a planning heuristic. The acceptable residual must come from the channel model and the supplier’s depth-control capability.

Zpětné vrtání

Back-drilling removes the unused plated barrel with a controlled-depth secondary drill. The design must define the drilled side, target layer, nominal remaining stub, allowed depth tolerance, drill oversize, keep-out to adjacent features and verification method. X-ray, process coupons, microsection or machine depth records may be used depending on the quality plan. “X-ray verified on every board” should not be promised unless the order explicitly requires and prices that sampling.

Blind vias and HDI

Blind microvias can shorten transitions and improve breakout density, but stacked structures introduce interfacial reliability considerations. The via type is chosen from BGA escape, layer reach, routing and qualification-not only from data rate. A conventional through via with a well-designed antipad and back-drill can outperform a poorly qualified stacked microvia.

Reference transitions

When a signal changes layer, its return current needs a nearby path between the old and new reference planes. If both references are ground, stitching vias can provide that path. If the reference changes between power and ground, a properly placed decoupling path may be needed. The spacing is determined by transition geometry and frequency; a universal 50 mil rule is not a substitute for analysis.

Figure 3. 10 layer high-speed PCB stackup and channel review.

Pre-Fabrication and Post-Fabrication Verification

Před výrobou

Pre-fabrication review should confirm the stackup, material constructions, impedance classes, copper model, critical via transitions, back-drill definition and coupon plan. For the highest-speed links, compare post-layout extraction with the compliance model and include manufacturing corners rather than only nominal geometry.

Po výrobě

Standard bare-board records can include electrical test and controlled-impedance results when ordered. High-speed programs may additionally request insertion-loss coupons, back-drill measurements, microsections, material certificates or first-article S-parameter data. The required document package should be agreed before quotation; it is not realistic to claim that every advanced report ships with every board.

IPC-TM-650 includes methods for characteristic impedance and signal-loss testing, but the customer still has to define the representative coupon, acceptance limit, sampling and lot disposition. For a compliance-critical product, correlate coupon data with the extracted route model rather than treating the coupon as a stand-alone certification.

Information Required for a High-Speed Fabrication Quote

A quote can be fast only when the technical package is complete. Supply native fabrication data, drill and route files, netlist, released stackup or stackup constraints, impedance table, material approval rule, copper requirement, back-drill drawing, controlled-depth definitions, surface finish, board class, quantity and required reports.

For channel-sensitive designs, also provide the interface/form-factor specification, critical layer assignments, maximum route or extracted loss targets, any prohibited material or glass styles, and whether the fabricator may adjust controlled geometry. Identify features that require customer approval before CAM changes.

The manufacturing route and records are described in the 10 layer manufacturing guide. Cost should be evaluated from the complete construction, not from a fixed “high-speed surcharge.”

Request a High-Speed 10 Layer PCB Review

Model Manufacturing and Operating Corners

A nominal channel result is not enough for a production release. The extracted model should include realistic high- and low-loss corners: dielectric thickness, Dk/Df, etched width, copper roughness, via registration and back-drill residual. Temperature can also alter dielectric behavior and receiver margin. The purpose is not to combine every worst case unrealistically, but to identify the variables that dominate margin and confirm that the procurement tolerance controls them.

Correlate simulation and fabrication data at first article. A TDR coupon can validate impedance, a loss coupon can validate the chosen dielectric/copper model, and a back-drill coupon or microsection can validate the residual-stub assumption. When the measured data differs from the model, update the model or process before using the construction as a reusable high-speed platform.

Protocol compliance remains a system responsibility

A bare-board supplier can verify construction, electrical continuity, representative impedance and agreed coupons. It cannot certify a complete PCIe, Ethernet or memory link without the assembled devices, packages, connectors, firmware and compliance test setup. Website language should distinguish “manufactured to the customer’s released high-speed requirements” from “protocol certified.”

Standards Status and Implementation Boundaries

Interface names must be tied to the revision and form factor used by the product. PCI Express 7.0 Version 1.0 was released in 2025, while the board-level limits still depend on the applicable base and form-factor documents. IEEE 802.3df-2024 covers 400 Gb/s and 800 Gb/s Ethernet. Work on 1.6 Tb/s Ethernet and additional 200/400/800 Gb/s physical layers continues under IEEE P802.3dj, so a design based on that work must identify the exact draft or customer specification used. OIF 224G-class projects likewise define multiple reach categories rather than one universal PCB channel.

This distinction matters to fabrication because loss masks, package assumptions, connectors, test fixtures and equalization differ by implementation. A supplier should never convert “800G,” “1.6T” or “224G” into a fixed material, trace length or back-drill value without the governing channel definition.

High-Speed Channel Sign-Off

• Identify the interface revision, form factor, endpoints and compliance method.
• Allocate loss, return loss, crosstalk and discontinuity margin across packages, board, vias and connectors.
• Select laminate, copper profile and geometry from the extracted channel rather than from the protocol label.
• Model manufacturing corners for dielectric thickness, Dk/Df, copper roughness, line width, via depth and registration.
• Define representative impedance and loss coupons separately from product-level compliance testing.
• Release the same stackup and pad-stack revisions to layout, simulation, fabrication and test teams.

From Simulation to First-Article Correlation

A channel model is most useful when the fabricated first article can be related back to its assumptions. The correlation plan should identify which dimensions and material variables will be measured, which coupons will be tested and how those results will update the model.

Correlation does not mean forcing measured data to match an optimistic model. It means updating the model with the actual manufactured construction and determining whether the channel still meets margin at process and operating corners. When correlation reveals that copper roughness, resin content or via depth differs from the assumption, the corrective action may be a material-control change, a transition redesign or a revised routing limit-not simply a tighter impedance tolerance.