Rialú Impedance PCB 10 Sraith agus Fíorú TDR

Controlled impedance is achieved by controlling a transmission-line structure, not by assigning a standard trace width to a protocol. The same 50 Ω target can require very different geometry on two ten-layer boards because dielectric thickness, copper thickness, material construction, solder mask and neighboring copper are different. A production drawing should therefore specify the target and the reference structure, while the released stackup and fabricator calculation define the final width and spacing.

This guide explains what must be calculated, what a fabrication tolerance actually applies to, and how a TDR coupon should represent the routed structure. It deliberately avoids publishing universal “5 mil equals 50 Ω” rules, because those numbers become wrong as soon as the construction changes.

Controlled Impedance Is a Stackup and Process Definition

The characteristic impedance of a PCB trace is set by the distribution of electric and magnetic fields around the conductor. The dominant inputs are the finished conductor cross-section, distance to one or more reference planes, dielectric properties, pair spacing for coupled lines, solder mask on surface structures and the presence of nearby copper. Copper roughness and dielectric loss affect propagation and measured response, particularly as edge rate increases.

A controlled-impedance order should answer two different questions. First, what geometry is expected to meet the target on the chosen stackup? Second, how will production be verified? Field-solver calculation addresses the first; a representative coupon and TDR procedure address the second. Neither replaces a channel simulation when insertion loss, via discontinuities and connectors are important.

An Cruacháil 10 shraith must be frozen before the routed geometry is frozen. If the fabricator changes a core, prepreg, copper foil or pressed thickness, the impedance calculation must be updated and any resulting artwork change must follow the agreed approval process.

Inputs Required Before Trace Geometry Can Be Released

For differential pairs, the fabricator should receive width and spacing as variables rather than an immutable artwork rule when the stackup is still being finalized. The released drawing can authorize controlled width adjustment within stated limits, or it can require customer approval before artwork changes.

Single-Ended, Odd-Mode and Differential Impedance

A single-ended target such as 50 Ω describes one conductor relative to its return structure. A differential target such as 85 Ω or 100 Ω describes the voltage difference between two conductors driven in opposite directions. For a symmetric coupled pair, differential impedance is approximately twice the odd-mode impedance. It is not necessarily twice the single-ended impedance of either trace when the other trace is absent.

Strong coupling allows a narrower pair spacing and can lower differential impedance, but it also makes the result more sensitive to spacing variation and local pair separation. Weakly coupled pairs are influenced more by their reference planes and less by the exact gap, but may consume more routing width. The right balance depends on routing density, skew, crosstalk to neighboring channels and the fabricator’s etch capability.

Common-mode impedance and mode conversion can matter even when the differential TDR number passes. Asymmetrical breakout, unequal via antipads, different reference transitions and one-sided tuning can convert differential energy into common mode. At high data rates, a 3D transition model is more informative than a single coupon number.

Microstrip, Stripline and Coplanar Structures

Outer-layer microstrip

Microstrip is easy to probe and route but its fields extend into both laminate and air or solder mask. The effective dielectric constant is therefore lower than the bulk laminate Dk. Solder mask, surface finish, local copper pours and component pads can all perturb the result. Outer-layer plating also changes conductor thickness after the base foil is selected.

Embedded microstrip and stripline

Embedded microstrip is covered by dielectric on both sides but is referenced primarily to one plane. Stripline lies between two planes. Symmetric stripline has equal or near-equal dielectric spacing; asymmetric stripline has a dominant nearer reference but still interacts with both planes. A field solver should model both boundaries and the actual trace position after lamination.

Coplanar waveguide structures

Coplanar ground can control field spread and provide shielding, but the gap to side copper becomes another critical dimension. Ground islands must be connected to the reference plane with an appropriate via pattern or they can behave as resonant conductors. Coplanar structures should be modeled with the actual mask and ground geometry rather than appended as a generic “ground pour” rule.

Manufacturing Variation and a Realistic Tolerance Budget

Production impedance moves because several dimensions move together. Etching changes the top and bottom width. Lamination changes pressed dielectric thickness. Resin content and glass distribution affect effective Dk. Outer-layer plating and solder mask add more variation. A responsible tolerance analysis uses the supplier’s process capability for the exact construction rather than assuming every input can be held at its nominal value.

+/-10% is a common procurement tolerance, but it is not a universal default imposed by an IPC document. Tighter bands may be feasible on selected structures and panel sizes, while some high-impedance, very fine or heavily plated structures can be less capable. Before specifying +/-5% or tighter, confirm the available geometry margin, coupon method, lot sampling and whether the tolerance is measured on the coupon or guaranteed at every routed location.

Tightening impedance without a channel-level reason can increase scrap or force a wider trace/space geometry that harms routing density. Conversely, a nominal +/-10% coupon may be inadequate where connector, package and via discontinuities leave little system margin. The tolerance should come from the electrical budget and the manufacturing capability study.

Coupon Design and TDR Verification

IPC-2141 is a design guide for controlled-impedance circuits; it is not the TDR test method. Characteristic impedance measurement by time-domain reflectometry is covered by IPC-TM-650 Method 2.5.5.7A. A purchase order should cite the applicable method or an agreed customer procedure and then define the coupon and acceptance details that the method alone does not decide.

A representative coupon

The coupon should use the same layer, reference structure, copper processing, dielectric construction and solder-mask condition as the controlled route. Differential coupons should reproduce pair width and spacing. When multiple structures exist, one coupon trace cannot represent all of them. Coupon location on the production panel matters because plating and etch can vary across the panel.

Measurement window and launch

The launch, probe pads and initial discontinuity must be separated from the uniform section used for the impedance reading. The TDR rise time should be appropriate for the feature being measured; an excessively fast edge can emphasize small discontinuities, while a slow edge can average them out. Loss and dispersion can create a sloped trace, so the acceptance window and reporting method should be agreed.

Sampling and records

“Per panel,” “per lot” and “first article only” are commercial and quality-plan choices, not automatic consequences of a tolerance value. Specify the number and location of coupons, destructive or retained status, lot definition, re-test rule and whether plots or summary results are required. For high-reliability programs, preserve traceability between coupon, panel and shipped boards.

How to Specify Impedance on the Fabrication Drawing

The impedance table should be unambiguous enough that engineering, CAM and inspection teams interpret it the same way.

Keep protocol routing rules on the layout or design specification and keep impedance acceptance on the fabrication drawing. This separation prevents a supplier from interpreting “PCIe” as a complete electrical requirement.

For artwork review, use the 10 layer routing guide; for fabrication variables and documentation, see the treoir phróiseas déantúsaíochta.

Diagnosing an Impedance Result That Misses the Target

A failed coupon should trigger a structured investigation rather than an immediate line-width change. Confirm that the coupon matches the board structure, the correct stackup revision was used, the TDR launch and measurement window are valid, and the reported result is not dominated by excessive loss or a probe discontinuity. Then compare actual trace cross-section and dielectric thickness with the solver model.

Low measured impedance can result from a wider trace, thinner dielectric, higher effective Dk, thicker copper, closer coplanar ground or additional solder mask. High impedance can result from the opposite conditions. Differential results can move because of pair spacing even when each trace width is correct. Microsection data and a recalculated model are more useful than changing one input by guesswork.

If the miss is systematic, update the process-calibrated model and artwork compensation. If it is localized by panel position, investigate etch, plating or lamination uniformity. Any rework or use-as-is disposition should consider the system margin, not only the coupon percentage.

Submit a Stackup and Impedance Table for Review

Frequency, Loss and the Meaning of the TDR Number

Characteristic impedance is often presented as one number, but a real interconnect is dispersive and lossy. Dielectric properties, copper roughness and skin effect change with frequency, so the apparent TDR trace can slope along a long coupon. A short uniform section may read differently when measured with a different edge rate or de-embedding method. The acceptance procedure should therefore define where and how the value is read rather than relying on a screenshot alone.

A passing impedance coupon does not prove low insertion loss. Two traces can both measure 50 Ω while one uses rough copper and a higher-loss dielectric. Conversely, a lossy trace can make the far end of a TDR waveform appear different even when its physical geometry is uniform. When channel loss matters, use an appropriate signal-loss coupon or S-parameter measurement in addition to TDR.

Differential coupon pitfalls

Differential TDR requires balanced launches and equal electrical length to the measurement section. Probe-pad asymmetry, unequal fanout or a reference-plane opening can create mode conversion that looks like a pair-impedance problem. The coupon should include enough uniform length to separate the launch from the evaluation window and should reproduce the actual mask and reference structure. Reporting both differential and, where useful, common-mode behavior can reveal an asymmetry hidden by a single average value.

Production correlation

When a new stackup is introduced, correlate TDR results with microsectioned trace width, copper thickness and dielectric spacing. That correlation creates a more reliable process model for later lots. If a supplier changes material construction, foil or press cycle, the correlation should be reviewed rather than assuming the previous compensation still applies.

Tight-Tolerance Feasibility and Artwork Authority

A tighter number is not always a better specification. The achievable distribution depends on trace width, dielectric height, copper thickness, panel position, etch process and whether the structure is surface plated. Very narrow traces can show a large percentage change from a small absolute etch variation; very high-impedance lines may require widths or dielectric gaps that are impractical. The fabricator should review a tolerance as a process-capability question, not merely accept it as a sales option.

Before release, agree who controls artwork. One method is for the customer to supply nominal geometry and authorize the fabricator to compensate width and pair gap to the released stackup. Another is to freeze geometry and require the supplier to match the construction exactly. Mixing the two approaches creates disputes when a supplier adjusts line width but the layout clearance, skew or crosstalk model assumed the original geometry.

For a new construction, consider a first-article capability run with coupons across representative panel locations. Use the measured distribution to set a realistic production control plan. A single passing coupon cannot establish long-term capability, while a statistically justified process may support a tighter band without excessive inspection.

Impedance Release Checklist

An impedance requirement is complete only when the target, transmission-line structure, manufacturing authority and verification plan are all defined. A drawing that lists “50 Ω” or “100 Ω differential” without layer, reference, tolerance and mask condition leaves the supplier to make assumptions.

• Identify each impedance class by signal layer, reference plane or planes, target, tolerance and structure type.
• Provide nominal geometry as design intent and state whether the supplier may adjust width or pair spacing.
• Model pressed dielectric, finished trapezoidal copper, solder mask and nearby copper.
• Use construction-specific material data or a documented fabricator design-Dk model.
• Design coupons that represent the actual production structure and define the TDR method, sample frequency and report content.
• Keep coupon impedance verification separate from channel insertion-loss, via and connector compliance.

Tight tolerance should be justified by channel sensitivity and demonstrated process capability. It is not a substitute for a continuous return path, a good via transition or a complete loss model.

Measurement Uncertainty and Coupon-to-Product Correlation

A TDR result is affected by the coupon, launch, fixture, instrument bandwidth, reference-plane quality, calibration and the method used to choose the reported impedance region. Two laboratories can measure the same coupon differently if these conditions are not aligned. The acceptance procedure should therefore define more than the target and tolerance.

• Identify the test method or customer procedure and the instrument/calibration expectations.
• Define coupon length, launch removal or gating approach and the region used for the reported value.
• Keep the coupon on the same panel construction, layer, copper and reference system as the product structure.
• Record whether the reported value is an average, median, windowed result or another agreed statistic.
• Define how outliers, damaged coupon launches and retest are handled.

Coupon correlation also has limits. A long straight coupon does not include every pad, neck-down, via, connector launch or plane opening on the product. Those discontinuities belong in the channel model or a dedicated test structure. Conversely, adding complex product features to the impedance coupon can make it difficult to separate process impedance from a deliberate discontinuity.

For tight-tolerance programs, correlation should compare measured coupon geometry and microsection data with the field-solver model. If impedance is high or low, the review should consider pressed dielectric, conductor top/bottom width, copper thickness and material construction before changing artwork. Adjusting trace width without identifying the physical cause can make one lot pass while weakening repeatability.