10-lagers PCB-tillverkningsprocess från DFM till inspektion

A ten-layer printed circuit board is manufactured through a controlled sequence in which every operation affects the next one. Inner-layer artwork compensation influences registration after lamination; lamination determines dielectric thickness and drill alignment; drilling and desmear affect copper adhesion; plating changes finished conductor geometry; and the final electrical and structural tests verify whether the accumulated process remained inside the released design window. Treating these operations as an independent checklist hides the most important manufacturing fact: multilayer yield is created by managing the interfaces between steps.

This article describes a conventional rigid ten-layer process first, then explains where HDI, rigid-flex, mixed-material and special-feature constructions diverge. It does not present one fixed press temperature, one universal drill speed or one mandatory sampling plan, because those parameters depend on the selected material system, board geometry, product specification and qualified factory process. The project-specific traveler is created after DFM-granskning and becomes the controlling manufacturing instruction.

Highleap Electronics provides multilayer PCB-tillverkning, but the customer and fabricator must jointly define the released stackup, tolerances, via structures, acceptance class and documentation. The broader 10 layer PCB engineering overview explains stackup and procurement choices; this page follows the board through production.

Engineering Release: What Must Be Resolved Before Production

Manufacturing does not begin when Gerber files arrive. It begins when the incoming data has been converted into an approved, internally consistent fabrication package. Most expensive ten-layer mistakes originate before imaging: an undefined via start layer, a trace width that conflicts with finished copper, a stackup that does not close to the required thickness, or a material substitution that changes impedance after the layout has been frozen.

Data set normally required

• Gerber X2, ODB++ or IPC-2581 layer data with unambiguous layer order;
• NC drill and route files separated by hole type and start/stop layer;
• fabrication drawing with finished thickness, finished copper, board outline, tolerances, finish and acceptance requirements;
• stackup or stackup constraints, including impedance reference layers;
• controlled-impedance table with layer, geometry, target and tolerance;
• via-fill, back-drill, countersink, edge-plating, castellated-hole or depth-routing notes where applicable;
• material specification and substitution policy;
• panel or delivery-array requirements;
• marking, serialization, traceability and report requirements;
• assembly profile or special reliability requirements when they influence bare-board qualification.

CAM and DFM checks

The CAM team verifies netlist consistency, drill-to-copper clearances, annular lands, solder-mask registration, copper-to-edge spacing, routability, coupon placement, copper balance and the interaction between the board outline and the proposed production panel. Controlled-impedance structures are recalculated using the proposed material constructions and finished copper. When the supplier changes a line width or spacing to meet impedance, the change should be returned for approval rather than silently embedded in production data.

For a ten-layer board, the DFM output should answer at least five questions:

1. Can the proposed stack be built to the finished thickness and tolerance?
2. Can every drilled structure meet registration, annular-ring and aspect-ratio requirements?
3. Can the required conductor geometry still be etched after the necessary plating?
4. Are the impedance values achievable with available material constructions?
5. Do the specified tests and reports match the product class and purchase documents?

Production panel design

The individual board is nested into a manufacturing panel with tooling holes, registration targets, plating thieving, coupons, test structures and process margins. Panel orientation can affect dimensional movement, glass-weave direction, routing yield and bow/twist. The panel is not merely a way to fit more pieces into a sheet; it is the process vehicle used by imaging, drilling, plating and test equipment.

Inner-Layer Imaging, Etching and AOI

Each internal copper pattern begins on a copper-clad core. The core is cleaned, coated with photoresist, imaged, developed, etched and stripped. The finished conductor width is the result of artwork compensation, copper thickness, resist chemistry, exposure, developer condition, etchant chemistry and spray dynamics. A blanket statement that every trace is held to a single tolerance is therefore misleading; capability depends on the geometry and copper construction.

Material preparation and identification

Cores are issued by material type, thickness, copper weight, glass style and lot. Controlled material projects may require positive identification and lot traceability before the panels enter imaging. Surface contamination, oxidation or storage damage can reduce photoresist adhesion and later interlaminar bond strength, so handling and bake requirements follow the laminate supplier’s processing guidance and the factory’s qualified procedure.

Direkt laseravbildning

Laser direct imaging exposes the resist from digital artwork and avoids dimensional errors associated with film masters. The system aligns the pattern to panel targets and applies scale compensation derived from material and process history. Registration capability depends on panel size, core thickness, material stability, target quality and the equipment in use; it should not be reduced to one universal micrometre value.

Etching and conductor compensation

Inner-layer copper is chemically removed from unprotected areas. Because etching also attacks conductor sidewalls, the CAM artwork is widened by an amount appropriate to the copper thickness and etch process. Fine lines on thicker copper require more compensation and can develop trapezoidal profiles that affect impedance. This is one reason a nominal line width in the design file is not necessarily the final production artwork width.

Automatisk optisk inspektion

AOI compares the etched panel with approved digital data and flags opens, shorts, nicks, protrusions, residual copper and other pattern anomalies. AOI is commonly applied to all inner-layer panels, but AOI acceptance does not prove dielectric quality, plating integrity or completed-board reliability. Detected defects are reviewed under controlled procedures. Repair policies should be defined by the factory quality system and customer requirements; a hidden conductor repair must never be assumed acceptable for a high-reliability product.

Bond Treatment, Layup and Lamination

After inner-layer acceptance, copper surfaces are prepared to bond to the resin system. The treatment must provide adhesion without creating an excessive profile that degrades high-speed conductor loss. Conventional oxide, reduced oxide and oxide-alternative processes can all be suitable when they are qualified with the chosen material.

Layup architecture

A ten-layer stack may be built from several cores and prepreg interfaces, or from a combination of cores and outer copper foil. There is no universal requirement for “five cores.” The number depends on the stackup architecture. For example, some designs use four double-sided cores for L2-L9 plus outer foil, while others use different core pairings to control dielectric availability or buried-via construction. The layup sheet must match the approved layer order exactly and identify material, glass style, resin content, copper and orientation for every interface.

Why a fixed press recipe is wrong

Press temperature, pressure, vacuum, ramp, dwell and cool-down are selected from the laminate supplier’s cure requirements and the fabricator’s qualified recipe. A generic statement such as “200 deg C, 350 psi for 90 minutes” is not appropriate across high-Tg FR-4, low-loss PPE systems, polyimide, PTFE-based hybrids or mixed constructions. The cure cycle must achieve resin flow, void removal and full cure without excessive squeeze-out, resin starvation or uncontrolled dimensional movement.

Lamination controls

• material and lot verification before layup;
• clean-room or controlled-environment handling appropriate to the process;
• book orientation and copper-balance review;
• vacuum and press-profile monitoring;
• resin-flow and thickness prediction;
• registration target inspection after press;
• finished panel thickness and bow/twist checks;
• coupon or first-article sectioning when required.

Common lamination defects

Voids can result from trapped air, contamination or inadequate resin flow. Resin starvation occurs where dense copper, large fill features or excessive pressure leaves insufficient dielectric. Delamination may originate in poor surface preparation, moisture, incompatible materials or incorrect cure. Excessive resin flow can change dielectric thickness and impedance. Inner-layer misregistration can come from artwork scaling, tooling, panel movement or asymmetric construction. Each defect has a different root cause; none is solved by quoting a higher nominal Tg alone.

Mechanical Drilling, Laser Drilling and Depth-Controlled Features

Drilling establishes the interlayer connection geometry. The fabrication data should separate plated through-holes, non-plated holes, buried holes, blind mechanical holes, laser microvias, back-drills, countersinks and controlled-depth routes. Combining these into one undifferentiated drill table is a common source of manufacturing questions and incorrect tooling.

Mekanisk borrning

Carbide tools are selected by finished hole size, material, panel stack, required wall quality and positional tolerance. Spindle speed, infeed, chip load, backup and entry materials are process variables rather than fixed values. Very small mechanical drills may require reduced panel stacking and shorter tool life. Ceramic-filled or high-frequency materials can increase wear and demand different tool geometry. The supplier must also account for plating allowance: the drilled diameter is larger than the finished plated-hole diameter.

Drill registration and smear

The drilled hole must remain inside the inner-layer capture land after all imaging, lamination and drilling tolerances are combined. Thick boards, small holes and high layer counts reduce the available annular-ring margin. Heat and mechanical action during drilling can smear resin over exposed inner-layer copper, so hole-wall preparation is essential before metallization.

Laserborrning

HDI microvias are typically formed with CO2, UV or combined laser processes selected for the dielectric and copper structure. CO2 systems are widely used for resin-based buildup dielectrics, often with copper-opening preparation; UV can process copper and dielectric with fine control. The best route depends on hole size, target depth, reinforcement, copper-opening method, throughput and qualified equipment. Blanket claims that one wavelength is always required for a given nominal diameter should be avoided.

Bakborrning

Back-drilling removes the unused portion of a plated through-hole after the board’s layer connections are known. Tool diameter, entry side, stop depth and allowable remaining stub must be documented. The achievable residual stub depends on layer location, board thickness, depth-control method, registration and verification. A universal “four mil from the signal layer” rule is not appropriate; the design needs a safe clearance to the connected layer while meeting the channel’s stub target.

Other controlled-depth features

Counterbores, countersinks, cavities, coin pockets and depth-routed channels require separate mechanical data and tolerance definitions. Their sequence may affect plating, solder mask and final profile. A depth callout should identify the datum surface, target depth or remaining thickness, tolerance and whether the feature is plated.

Desmear, Electroless Copper and Electroplating

After drilling, the hole wall is nonconductive and may contain resin residue, glass protrusion and mechanical debris. Hole-wall preparation and metallization create the conductive path that later electroplating builds to the required thickness.

Desmear and conditioning

Permanganate, plasma or combined processes remove smear and condition the dielectric. The chemistry must be matched to the resin system; over-processing can attack dielectric or glass interfaces, while under-processing can leave contamination on inner-layer copper and weaken the interconnect. Low-loss and mixed-material constructions may require special conditioning because their resin chemistry differs from conventional FR-4.

Initial conductive layer

Electroless copper or a qualified direct-metallization process deposits a thin conductive film on the prepared hole wall. The purpose is to create continuous conductivity for electrolytic plating. A single nominal thickness is not universal across processes; coverage, adhesion and continuity are more important than quoting a generic number without the governing specification.

Electrolytic copper plating

Electroplating builds copper in the barrel and on exposed surface copper. Throwing power becomes more difficult as the hole aspect ratio increases. Current density, agitation, chemistry and panel current distribution are controlled so the center of the hole receives adequate copper without excessive surface buildup. Product acceptance is evaluated against the governing performance specification and purchase documentation, not against an isolated marketing value.

Microvia filling

Filled microvias use plating chemistry designed to preferentially fill from the bottom while minimizing voids, seams and excessive surface copper. When another microvia will be stacked above, the filled surface must be sufficiently planar for the next dielectric and target pad. The allowable dimple or bump and the inspection method should be defined. A filled microvia process is different from plugging a through-hole with resin and plating a cap over it.

Outer-Layer Imaging, Pattern Plating and Etching

Outer-layer processing differs from inner-layer subtractive etching because the plated holes and surface conductors are commonly built during pattern plating. A typical process images the outer pattern, plates copper in exposed areas, applies an etch resist such as tin, strips the photoresist, etches unwanted base copper and then removes the etch resist. Alternative qualified processes may be used, but the sequence must preserve hole-wall and conductor requirements.

Finished copper must be known before artwork is released

The outer conductor does not equal the starting foil thickness. Hole plating and pattern plating add copper, and via-fill or wrap-plating processes can add more. Fine-line capability must therefore be assessed against finished surface copper, not a catalog foil value. This is particularly important on HDI boards, where repeated plating can narrow the etching window.

Yttre lager AOI

After etching, outer layers are optically inspected for opens, shorts, conductor damage, residual copper and pad anomalies. AOI data does not replace electrical testing because some defects may be hidden, intermittent or related to hole interconnects. It is one stage in a layered verification strategy.

Edge plating and castellations

Plated edges and castellated holes require the profile and plating sequence to be coordinated. Edge-plating areas may be routed before plating and finished later. Castellations require hole placement and final routing that leave the specified plated half-hole geometry. These features should be shown on the drawing and cannot be safely inferred from copper artwork alone.

Solder Mask, Legend, Surface Finish and Profiling

Solder-mask preparation and imaging

The copper surface is cleaned, liquid photoimageable mask is applied, tack dried, imaged, developed and fully cured. Mask registration is evaluated against pad size, mask-defined or non-mask-defined land strategy, via tenting requirements and component pitch. A fixed mask thickness range is not appropriate for every ink, feature and location; the product specification and approved material control the requirement.

Legend and marking

Legend must remain clear of exposed pads, test points and critical lands. Serialization, date code, lot code, UL mark and customer identifiers are placed according to the fabrication drawing and traceability plan. Marking content should be approved before production because adding or moving codes after fabrication may violate customer-controlled artwork.

Surface-finish selection

The finish protects exposed copper and provides the interface for soldering, wire bonding or wear contacts. Selection is based on assembly method, component pitch, storage, RF loss, contact wear and regulatory requirements.

• ENIG: planar and widely used for fine-pitch assembly. Requirements should reference the applicable revision of IPC-4552 rather than rely on a simplified marketing thickness.
• ENEPIG: supports soldering and certain wire-bonding applications when specified and controlled under IPC-4556.
• OSP: thin organic protection suitable for compatible assembly and handling conditions.
• Immersion silver or immersion tin: selected for specific assembly, press-fit or electrical requirements, with storage and handling controls.
• HASL: robust for many through-hole and larger-feature applications but less planar than immersion finishes.
• Electroplated hard gold: used selectively on wear contacts such as edge fingers; nickel and gold thickness are specified for the contact application.

Finish thickness verification follows the applicable finish specification and agreed sampling plan. It should not be advertised as XRF measurement of every pad or every board unless that is actually required and performed.

Final profiling

Routing, punching, laser cutting or V-scoring separates the board or creates the delivery array. The drawing should define final dimensions, edge tolerances, tabs, breakaway rails, V-score remaining thickness and component-to-edge restrictions. Bow and twist are evaluated on the finished board or array under the governing acceptance requirements.

Electrical Test, TDR and Structural Verification

Electrical continuity and isolation

Unpopulated-board electrical testing verifies that intended networks are connected and unintended networks remain isolated. Flying-probe equipment is common for prototypes and low volume because it avoids a dedicated fixture. Fixture testing can improve throughput for stable production volumes. Test parameters, data and coverage should comply with the purchase specification and applicable IPC-9252 requirements. Throughput and fixture cost are design-dependent and should not be stated as universal values.

TDR impedance verification

Controlled-impedance boards are verified on designed coupons using time-domain reflectometry. The coupon must reproduce the relevant layer, copper, dielectric and reference configuration closely enough to represent the product structure. IPC-TM-650 2.5.5.7A describes TDR measurement methods, while coupon geometry, frequency of test, acceptance tolerance and reporting are controlled by the order documentation. There is no general rule that +/-5% requires “one coupon per panel half” or +/-3% requires “one per panel quarter.”

Microsection and structural evaluation

Representative coupons are prepared, polished and examined for layer registration, hole-wall copper, internal connections, dielectric condition, microvia fill, wrap plating and other structural attributes. The sample plan comes from the governing product specification and purchase documentation. IPC-A-600 is the illustrated interpretation of observable acceptance conditions; the actual performance requirements come from specifications such as IPC-6012, IPC-6013 or IPC-6018.

Thermal preconditioning and reliability testing

Some products require assembly-simulation reflow, thermal stress, thermal shock or electrically monitored cycling before structural evaluation. The method must be named and the profile, number of exposures, coupon and failure criterion defined. “Three-cycle microsection,” “1,000-cycle IST” and similar phrases are not universal substitutes for a written reliability plan.

How HDI, Rigid-Flex and Hybrid Materials Change the Flow

HDI sequential buildup

HDI repeats lamination, laser drilling, cleaning, metallization and often copper filling for each buildup level. The central subassembly may also contain buried vias. As buildup depth increases, registration compensation, surface copper and dimensional movement become more difficult to control. The 10 layer HDI engineering guide explains how 1+8+1, 2+6+2 and 3+4+3 differ.

Styv-flex konstruktion

Rigid-flex processing introduces polyimide cores, coverlay, adhesive or adhesiveless flex materials, selective rigid areas, low-flow bonding materials and controlled flex-to-rigid transitions. Press conditions are selected for the approved material system; a blanket maximum temperature is not valid across all constructions. The fabrication sequence must protect exposed flex zones, control resin flow and preserve bend-area copper geometry. Bend tests or dynamic-flex qualification are required only when specified by the design and product requirements, not automatically for every rigid-flex shipment.

Mixed high-speed and RF materials

Hybrid stackups combine materials with different resin systems, copper options, dimensional movement and surface treatments. Bond compatibility and z-axis expansion must be evaluated. Drilling and desmear may need material-specific settings, and the impedance model must use the actual design Dk for each dielectric. A material that processes “like FR-4” still requires its own qualified compensation and press data.

Heavy copper, copper coins and embedded features

Heavy copper changes etch compensation, resin filling and plane balance. Embedded coins or inlays introduce pocket machining, bonding and planarity controls. Embedded passive or active components require a separate process architecture and governing specification. These should be treated as engineered variants, not included casually in a statement that one standard flow supports every special feature.

Quality Records, Traceability and Shipment Release

The records delivered with a shipment should be defined in the purchase order or quality agreement. A standard commercial order may require a certificate of conformance and electrical-test confirmation. A controlled medical, automotive, aerospace or defense program may require material certificates, lot traceability, microsections, finish data, impedance results, first-article records or customer-specific forms. It is inaccurate to claim that every ten-layer shipment automatically includes every possible report.

Common record categories

• certificate of conformance;
• electrical-test certificate or summary;
• TDR report for specified impedance classes;
• material identity and lot traceability where required;
• microsection report under the agreed sampling plan;
• surface-finish measurement data when contractually required;
• back-drill or controlled-depth verification for critical features;
• RoHS, REACH or other declarations applicable to the supplied product;
• first-article or qualification records;
• serialization and production-lot traceability data.

Traceability level and retention

IPC-1782 provides a framework for traceability levels, but it does not create one universal ten-year retention rule for every PCB. Retention period, data granularity and access are determined by the customer contract, regulatory system and supplier quality procedure. The quote should identify any unusual retention or digital-record requirements because they affect administration and audit scope.

Slutlig utgåva

Shipment release confirms that required operations and inspections are complete, nonconformances are resolved, quantities match, packaging protects the finish and moisture-sensitive conditions where applicable, and the required documentation is attached or available. Packaging method, vacuum sealing, desiccant, humidity indicator and shelf-life marking depend on finish, storage period and customer specification.

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