Painéalú PCB le haghaidh Táirgeadh Toirte: Costas agus Toradh

A fabrication panel that holds more boards is not necessarily the more economical panel. If its defect exposure, inspection time or downstream assembly losses are higher, its cost per accepted PCB can be worse even when the nominal cost per panel is lower.

This analysis of PCB panelization for volume production compares layout alternatives using a common denominator: good circuits actually delivered under the agreed acceptance rules. A worked hypothetical cost model shows why panel price and geometric area utilization are insufficient on their own.

For layout terminology, start with the PCB panelization fundamentals. The figures below are model assumptions rather than Highleap operating yields or guaranteed prices; replace them with actual production evidence before selecting a layout.

Separate Fabrication Panels, SMT Arrays and Delivery Units

A fabrication working panel is the substrate area processed through PCB manufacturing. It may hold multiple customer arrays, process margins, test coupons or tooling features; its arrangement is often constrained by the fabricator’s equipment. An SMT assembly array is what the placement line or fixture handles, commonly with rails, fiducials and a fixed X-by-Y map. A delivery unit might be one array, a carton of singles or a purchasing SET. Confusing these three levels makes a per-panel price impossible to evaluate fairly.

For tiny boards whose edge or SMT design determines the array style, first settle the basic layout constraints in the small PCB panelization walkthrough. The optimization method here assumes candidate arrays have already passed initial design and equipment feasibility checks.

Calculate Cost per Accepted Circuit

A supplier may offer a lower price per working panel for an aggressively nested layout. That does not prove a lower delivered PCB cost. At minimum, calculate the expected cost per accepted circuit for each qualified alternative. At the fabrication stage, a simplified planning equation is:

Estimated fabrication cost per accepted circuit = total relevant fabrication-panel cost ÷ expected accepted circuits from those panels.

For a stable per-panel model: Cost per accepted circuit ≈ cost per panel ÷ (circuits per panel × expected per-circuit acceptance fraction). This is an average planning approximation; it assumes the acceptance fraction can be applied to circuit positions and that costs for discarded workpieces are appropriately represented. It does not model correlated full-panel failures, repair policies, incomplete-array restrictions or mixed-revision scrap. Those effects must be reviewed separately.

A complete hypothetical comparison

Consider two already feasible layouts for one released PCB revision. All amounts and acceptance rates below are illustrative modeling inputs, not Highleap prices, yield claims or process capabilities.

Option B packs more circuits into one panel but produces a higher modeled cost per accepted circuit: $132 ÷ (18 × 0.94) ≈ $7.80 versus $84 ÷ (12 × 0.97) ≈ $7.22. At a 25,000-board planning quantity, that difference is material. It is not proof that all 18-up arrays are worse. Rather, it demonstrates why unit count alone is an inadequate purchasing criterion.

Sensitivity test: what would make Option B competitive?

Use Option A’s modeled cost per accepted circuit, about $7.216, as the target. With an $132 panel cost and 18 positions, Option B would require an acceptance fraction of approximately $132 ÷ (18 × $7.216) = 101.6%. That is impossible under these assumed costs. Therefore, for B to match A, at least one modeled assumption must change—its panel cost must fall, its number of circuits must rise, or A’s costs/acceptance must worsen. Increasing B’s acceptance from 94% to even 100% gives $132 ÷ 18 = $7.33 per accepted board, still above A’s assumed $7.22.

This type of sensitivity check turns vague phrases such as “improve yield” into a concrete decision threshold. However, comparing only fabrication cost is not enough if the array also moves through SMT or test.

Include Assembly Yield and Other Downstream Losses

A final production decision may need to combine fabrication, assembly, test, depaneling, packaging and nonrecurring costs. A broader model is:

All-in cost per shipped accepted product = (fabrication + assembly + test + approved rework/scrap + depaneling + packaging + amortized setup) ÷ accepted shipped products.

Avoid double-counting rejects already embedded in a supplier’s quoted delivered price. If the vendor quote is per accepted board, their internal fabrication yield may already be reflected in that price. If the buyer builds an internal bottom-up model, use the correct cost stage and denominator for each operation.

A second illustrative calculation: setup allocation

Suppose one array requires a $400 one-time fixture and the other a $1,000 fixture. The nominal setup allocation per accepted unit at 500 units is $0.80 versus $2.00. At 25,000 units it falls to $0.016 versus $0.040. A pilot order can therefore favor a different panel from a stable recurring production program—provided the new array’s qualification, machine programming and potential process changes are also accounted for.

An RFQ that simply asks for “the best panel price” cannot reveal these trade-offs. Ask for tooling/NRE separately, the number of accepted circuits priced and the test and delivery conditions included.

Account for Panel-Level Rejection

Not all defects affect one circuit independently. A local short might reject one board position. A plating, lamination or handling event could compromise multiple positions or a complete processed panel. An SMT stencil, fixture or oven issue can affect a joined array. Treating every failure as an independent 3% or 6% random event may therefore underestimate correlated loss.

Ask the manufacturer to distinguish per-position rejects ó panel-level rejects. Consider a hypothetical 18-up array where a panel-level defect invalidates all 18 positions: the expected loss from that one event is much larger than one bad isolated circuit. Some buyers also prohibit shipping an array with marked or missing positions; in that case, the accepted delivery unit may be the complete all-good array, not individual good circuits. Your denominator and rework/replacement policy must match the purchase order.

For purchasing terminology, the PCB SET delivery and panelization guide explains why “100 arrays” cannot automatically be equated with “1,800 good boards.”

Quality questions that affect panel economics

• Can the supplier ship an array with one failed position? If not, how is its value treated?
• Can a failed board be removed and another acceptable piece shipped separately, or must the array remain complete?
• At what stage are circuits electrically tested, and how are bad positions recorded?
• Are coupon and process-control regions included in the quoted panel quantity?
• Is the scrap allowance already priced in the accepted-board rate, or shown as a separate contingency?
• Does depaneling produce additional rejects, and who owns those losses?

There is no one correct response for all production programs. The contract must define which unit passes acceptance and which supplier provides the evidence.

Check Throughput and Equipment Fit

A high circuit count per array can reduce the number of loading operations, but only if the array remains compatible with the actual equipment. Conveyor width, oven support, stencil stiffness, placement travel, AOI field of view, test fixture capacity and depaneling cycle may each respond differently to larger arrays. The larger panel may also require more handling fixtures or special packaging.

A production review should request machine-facing information, not just a nested drawing. At the PCB stage, assess process-panel format, drilling and routing program, copper distribution and registration. At the assembly stage, assess stencil print and placement throughput, reflow support, inspection and rework access. At shipment, assess whether the accepted unit is a panel or singles, and which stage removes the rails.

An níos leithne SMT panelization constraints are useful background. A meaningful cost comparison records assumptions for the specific line rather than claiming that every additional board per array increases hourly output by the same percentage.

Freeze a Repeatable Panel for Volume Runs

A prototype panel proves that some boards can be made and handled. It does not automatically prove stability at volume. When introducing a production array, treat orientation, rail structure, tab positions, process coupons and inspection sampling as a controlled manufacturing package.

Release and qualification sequence

1. Freeze the product PCB revision. Ensure both panel alternatives use the same approved stackup, finish, holes and critical outline.
2. Document fabrication and assembly panel drawings separately where the manufacturing format differs from the customer array.
3. Validate assembly handling. Confirm conveyor, fixturing, stencil support, board orientation, depaneling accessibility and equipment clearances.
4. Define first-article evidence. Measure critical outline/edge features, verify accepted circuit count and review defects after the intended separation stage.
5. Run a meaningful pilot. Record actual process yield, rework time, panel failures and per-array handling rather than relying only on an assumed factory minimum.
6. Recalculate the cost. Replace estimates with qualified output and cycle data, and verify whether NRE or throughput changes the commercial choice.
7. Freeze the array revision. Require review for later changes to rails, tabs, orientation, panel size and delivery state, even if the single PCB data is unchanged.

For optical transport and network equipment, this control is useful when boards, line cards and host interfaces share an equipment platform but require different panel routes. The optical communication PCB service describes these equipment-board families.

Use the Same Cost and Acceptance Basis for Both Suppliers

Ask the supplier to show how proposed savings affect the approved design, not merely to quote a lower material price. A change to substrate, copper geometry, finish or critical edge may require requalification, eliminating the apparent procurement advantage. If you are evaluating a pluggable-module board, the optical transceiver PCB cost guide integrates panel choices with HDI, laminate and connector finishes.

Volume PCB Panelization FAQs

Is the array with the best board-area fraction always the most economical?

No. Geometric density ignores some of the process costs and all yield or assembly handling changes. Compare expected and then observed cost per accepted unit.

Should we optimize on cost per working panel or per delivery panel?

First determine the commercial acceptance unit. Working panels are internal manufacturing units; customers usually pay for accepted bare boards, acceptable finished arrays or agreed SETs. Normalize to that unit.

When should the panel layout be frozen?

After the real fabricator and downstream assembler have approved handling, separation and acceptance, and the first-article/pilot plan has established which change controls are required. A prototype layout alone is insufficient evidence for all programs.

Can an assumed yield number appear in an RFQ model?

Yes, if clearly identified as a scenario assumption rather than a historical factory capability or warranty. For an actual award decision, seek data that demonstrates the relevant process and production volume.

Request a Volume-Panel Review

To compare two layouts, send the released PCB drawings, candidate array drawings, target accepted-board quantity, assembly scope, delivery conditions and known handling restrictions. Highleap can review the specific quote assumptions and identify the checks needed before choosing a volume-production array. Highleap’s PCB quotation form.