Mazano Akanyanya Kubhadhara eFPGA Injiniya Inowana 700k pagore

Kune mainjiniya eFPGA ari kutsvaga kuwana muhoro wepamusoro, pane akati wandei akakosha mazano ekufunga. Chekutanga uye chepamusoro, kukudza hunyanzvi hwako muFPGA dhizaini nekusimudzira kwakakosha. Kuve nyanzvi mumitauro yakaita seVerilog neVHDL, pamwe nekugona maturusi ekusimudzira FPGA nemapuratifomu, zvinokuita iwe chinhu chakakosha mumunda.

Pave nemakore anopfuura gumi kubvira pandakatanga kusangana neFPGA mumazuva angu ekuyunivhesiti. Ndichiri kuyeuka kufara kwekupedzisa zviedzo zvakaita sedhijitari yekumira, quiz buzzers, uye password kukiya papuratifomu EDA kekutanga. Panguva iyoyo, ini ndakanga ndisati ndafumurwa kuHDL hardware tsananguro mitauro, saka magadzirirwo akavakwa achishandisa 74-yakatevedzana logic zvishandiso muMAX + plus II schematic nharaunda. Gare gare, panguva yezvidzidzo zvangu zvepashure nebasa rakatevera, ndakashandisa Quartus II, Foundation, ISE, uye Libero, uye ndakadzidzawo Verilog HDL mutauro. Kuburikidza nekudzidza uku, zvishoma nezvishoma ndakaonga hungwaru hweVerilog. Ndakaona kuti chidimbu chidiki chekodhi chaigona kupedzisa dhizaini yakaoma, uye kutakurika uye kushanda kwemutauro kwakasimba kupfuura izvo zvemagadzirirwo ehurongwa.

Kukosha kweMayero muFPGA Logic Dhizaini

Shamwari dzakashanda muindasitiri dzinoziva kuti makambani anosimbisa zviyero, kunyanya kune makuru madhizaini (ingave software kana hardware). Zvinenge zvisingabviri kuwana pasina kutevedzera zviyero. Logic dhizaini haina mutsauko: kana ukasatevedzera zviyero, unogona kuwana zvikanganiso kana uchigadzirisa mwedzi gare gare. Uchitarisa kumashure kune iyo kodhi yawakanyora, unogona kunge wakanganwa akawanda masaini mabasa, ndoda kutarisa kukanganisa. Kana mumwe munhu achibva pakati pepurojekiti, mutsivi angangofanira kutanga dhizaini kubva pakutanga. Kana iwe uchida kuwedzera maficha matsva kune yekutanga vhezheni, iwe unozonyanya kufanira kutanga patsva, zvichiita kuti zviome kuwana dhizaini reusability.

Panyaya yepfungwa, ndinofunga kuti zvinotevera zviyero zvakakosha:

1. Dhizaini Zvinyorwa: Mazano ekugadzira, akadzama kuita, nezvimwe, zvinofanirwa kunyorwa mumagwaro, uye chete mushure mekuongorora kwakasimba uye kubvumidzwa kunogona kuita nhanho inotevera yebasa. Iyi nzira inogona kuita kuti chirongwa chirambe chiri muchimiro chinodzoreka uye chinogoneka.
2. Code Standardization: Gadzirisa mazita echiratidzo, shandisa mavara madiki pamazita echiratidzo uye uppercase yemaparamita, tara yakaderera-chikamu masaini masaini ane _n pakupedzisira (semuenzaniso, rst_n), uye ronga masiginecha echiteshi nechiratidzo chimwe pamutsara kuti zvive nyore kuona kukanganisa mukusimbisa simulation.
3. Clock Domain Management: Shandisa wachi imwe chete yemodule yega yega, uye shandisa yakatsaurirwa module yewachi yekuzviparadzanisa nevamwe mumagadzirirwo anosanganisira akawanda mawachi madomasi kubvumira synthesizer kuti igadzirise mhedzisiro yakanyanya.
4. Dzivisa Combinatorial Logic yeLatches: Mumagadzirirwo eFPGA, zvinorambidzwa kushandisa yakachena combinatorial logic kugadzira latches. Latches ane D flip-flops anobvumidzwa, senge marejista ekugadzirisa.
5. Signal Synchronization: Kazhinji, masaini anopinda muFPGA anofanirwa kuwiriraniswa kutanga kuwedzera sisitimu yekushanda frequency.
6. Nyoresa Zvese Zvinobuda: Zvese zvinobuda zvemodule zvinofanirwa kunyoreswa kuti uwedzere kuwanda kwekushanda uye kuwana nguva yekusangana mukugadzira.
7. Dzivisa Wachi dzine Gedhi: Kunze kwekunge iri yakaderera-simba dhizaini, usashandise gated wachi, sezvo izvi zvichawedzera kusagadzikana kwedhizaini.
8. Clock Enable Signals: Hazvibvumirwi kushandisa zvikwangwani zvakakamurwa nemakaunda sewachi dzemamwe ma module. Pane kudaro, shandisa wachi gonesa masaini.

Nguva Dhizaini Yekuita Kwepamusoro

Mukuru wangu ane nhoroondo yekushanda kuHuawei neJunlong, saka zvakangoita, akatiudza nezve mamwe maitiro ekugadzira maitiro kuHuawei neAltera. Yedu mapurojekiti zviyero zvinoenderana nemaitiro eHuawei. Mumwedzi mishoma yadarika yebasa, chakanyanya kundiomesera chaive chirevo chiri paHuawei: nguva yakagadzirwa, isina kuedzerwa kana kugadzirwa. Mukambani yedu, purojekiti yega yega inoongororwa zvakasimba. Chete mushure mekudzokorora kwapfuura ndipo danho rinotevera rebasa rinogona kuitwa. Kutora logic dhizaini semuenzaniso, panzvimbo yekutanga kunyora kodhi ipapo, isu chekutanga tinoda kunyora iyo yakazara dhizaini dhizaini uye yakadzama logic dhizaini chirongwa. Mushure mekunge zvirongwa izvi zvaongororwa uye zvichionekwa sezvingabvira, kukodha kunogona kutanga. Kazhinji, nguva inoshandiswa pamabasa aya yakakura kudarika nguva inoshandiswa pakunyora kodhi.

Urongwa hwese hunonyanya kusanganisira kupatsanurwa kwemodule, masaini masaini uye nguva yekutanga-level uye yechipiri-level modules, uye maitiro ekuyedza dhizaini mune ramangwana. Mune iyi nhanho yehurongwa, zvakakosha kuve nechokwadi kuti nguva inochinjika kune yekutanga-chikamu module (uye pakupedzisira kune yechipiri-chikamu module). Izvi zvinorevei? Kana isu tikaita yakadzama dhizaini, isu zvirokwazvo tichaita zvimwe zvigadziriso kunguva yemamwe masaini. Nekudaro, izvi zvigadziriso zvenguva zvinogona kunyanya kukanganisa yekutanga-level module, kwete iyo yese dhizaini. Ndinorangarira pandakanga ndiri kuchikoro, nekuti ndaisanzwisisa dhizaini yenguva, ndaiwanzo gadzirisa nguva yemamwe masaini emodule nekuti nguva yechiratidzo haina kusangana, izvo zvaishungurudza.

Mune yakadzama logic dhizaini hurongwa, isu takatogadzira iyo interface nguva yedanho rega rega remamodule, uye kuti imwe neimwe nhanho yemamodule inoiswa sei inotemerwa. Nekuda kwekuti isu tawana izvi, kukodha kunowanzova nekukurumidza. Chinonyanya kukosha, nzira iyi inogona kuchengetedza dhizaini iri munzvimbo inodzoreka uye kudzivirira kudiwa kwekutanga dhizaini yese pamusoro nekuda kwekukanganisa munzvimbo imwechete.

Ndezvipi zvinhu zvinokanganisa kuwanda kwekushanda kwedunhu?

Iyo yekushanda frequency yedunhu inonyanya kuenderana nekunonoka kuparadzira chiratidzo pakati pemarejista uye wachi skew. Kana wachi iri muFPGA ichimhanya nemumitsetse mirefu, wachi skew idiki uye inogona kufuratirwa. Pano, kuti zvive nyore, chete zvinhu zvinokanganisa kunonoka kuparadzira chiratidzo zvinotariswa. Kunonoka kuparadzira chiratidzo kunosanganisira kuvhura nekuvhara kunonoka kwerejista, kunonoka kwenzira, uye kunonoka kuburikidza necombinatorial logic. Kuti tiwedzere kuwanda kwekushanda kwedunhu, tinofanira kushanda pane izvi zvinonotsa zvitatu uye kuita kuti zvive zviduku sezvinobvira.

1. Deredza Kunonoka neKuchinja Routing: Taura mafambisirwo emamwe masaini akakosha, senge wachi uye masaini ekudzora, kuti apfuure nepa FPGA zvishoma sezvinobvira. Izvi zvinogona kunyatso dzikisa kunonoka kwenzira.
2. Deredza Nhamba yeCombinatorial Logic: Shandisa kutarisa-kumusoro matafura (LUT) zvakanyanya sezvinobvira panzvimbo yemagedhi ane logic. Pamusoro pazvo, vamwe vanhu vanoshandisa marejista akadhindwa kuderedza kuwanda kwemagedhi, asi nzira yakanakisisa ndeyokushandisa mapaipi kuderedza kuwanda kwemagedhi.

Kazhinji, kuderedza huwandu hwemagedhi uye kuchinja nzira yekufambisa inzira dzinoshanda dzekuwedzera mashandiro edunhu. Mukugadzira chaiko, kazhinji musanganiswa wezvose zviri zviviri. Zvisinei, izvi hazvisizvo zvakakwana. Mune zvimwe zviitiko, kuchinja nzira yekufambisa kungasaderedza kunonoka, uye nzira inoshanda zvikuru ndeyekuderedza huwandu hwemagedhi.

Iwo Matambudziko eLogic Dhizaini: Sisitimu Architecture uye Simulation Verification

Pandakatanga kupinda mukambani iyi, mukuru wangu akandiudza kuti kuoma kwekugadzira dhizaini hakusi mukugadzirwa kweRTL-level kodhi, asi muhurongwa hwekuvakisa dhizaini uye simulation dhizaini. Parizvino, kuChina, kune kukoshesa kwakawanda pamagadzirirwo ekugadzira, asi zvinoita kunge pasina ruzivo rwakawanda pamusoro pedhizaini yedhizaini yedhizaini uye yekumisikidza ongororo, iyo inogona kuratidza yakaderera mwero wedhizaini muChina.

Pandakanga ndiri kuchikoro, ndaigara ndichifunga kuti chero bedzi RTL-level code yakaitwa zvakanaka, simulation verification yaingova muitiro, saka handina kuzvidza syntax yeHDL maitiro ekutsanangura uye ndakanga ndisingadi kudzidza nezve testbenches-nekuti ndaifunga. kudhirowa waveforms zvaive nyore; Ini hapana chandaiziva nezve system architecture dhizaini. Ndakatozosangana nezvimwe zvinhu pakambani iyi ndipo pandakaona kuti zvakanga zvasiyana zvachose.

Muchokwadi, munyika dzekunze, nguva uye manpower akashandiswa pakuenzanisa ongororo ingangove yakapetwa kaviri iyo yakashandiswa paRTL-level kodhi. Ikozvino, simulation verification ndiyo nzira yakakosha yekugadzira miriyoni-magedhi machipisi.

Simulation Verification: Modelling uye otomatiki

Kuomerwa kwekuenzanisira kwekufananidza kunonyanya kuve munzira yekuenzanisira kunyatso uye kunyatso simbisa iko kurongeka kwedhizaini (kunyanya kuwedzera kodhi yekuvhara). Mukuita uku, kukurumidza kwekuongorora kwakakoshawo.

Verification, mumashoko akareruka, inzira yekugadzira yakakwana kufukidzwa kwezvinosimudzira masosi uye wozoona zvikanganiso. Ini pachangu, ini ndinofunga kuti mukutevedzera simbisa, chinhu chakakosha kuita otomatiki yekusimbisa. Ichi ndicho chikonzero nei tichifanira kunyora testbenches. Mune imwe yeangu magadzirirwo azvino, zvinotora ingangoita awa imwe neimwe yekunyepedzera kumhanya (iyo iri chaizvo diki dhizaini). Sezvo kudhirowa waveforms isingakwanise kuwana verification otomatiki, kana tikatevedzera nekudhirowa waveforms, kutanga, waveform inokweverwa kurufu (kunyanya kune madhizaini ane yakaoma algorithms uye yekuisa nhamba yekugovera), chechipiri, kutarisa waveform ichave inouraya, uye yechitatu, mwero wekuona kukanganisa kunenge zero. Saka sei kuwana otomatiki? Nhamba yangu ichiri shoma, saka ndinogona kungotaura muchidimbu nezveBFM (modhi yebasa rebhazi).

Tichitora muenzaniso wekugadzira MAC musimboti (iyo yekumashure ibhazi rePCI), tinoda MAC_BFM, PCI_BFM, uye PCI_BM (PCI maitiro emhando). Basa guru reMAC_BFM nderekugadzira Ethernet mafuremu (stimulus sources), ine hurefu husina kurongeka uye furemu misoro, uye zvirimo zvakare zvakangoitika. Paunenge uchitumira, inokopawo kuPCI_BM; basa rePCI_BFM nderekufananidza maitiro ePCI bhasi, semuenzaniso, apo chigadziro chiri pasi pekuedzwa chinogamuchira furemu yakarurama, inotumira chikumbiro kubhasi yePCI, uye PCI_BFM ichaipindura uye inounza data mukati; basa guru rePCI_BM nderekuenzanisa zvinotumirwa neMAC_BFM nezvinogamuchira PCI_BFM. Sezvo iine ruzivo rwekutumira rweMAC_BFM uye ruzivo rwekugamuchira kwePCI_BFM, chero bedzi iyo dhizaini ine musoro, inogona kugara ichiongorora uye yakazara kana mudziyo uri kuedzwa uri kushanda zvakajairika, nokudaro uchiwana otomatiki kuona.

Huawei anofungidzirwa kunge ari kuita zvakanaka mukusimbisa simulation muChina. Vakagadzira chikuva chechokwadi chakanaka, uye mazhinji eBFM ane chekuita nekutaurirana akaitwa zvakanaka. Ndakanzwa kubva kushamwari yangu kuti ikozvino ivo vanongoda kuisa chishandiso pasi pekuyedzwa papuratifomu yekuyedza uye kugadzirisa ma paramita kuti aone otomatiki kana mudziyo uri muyedzo uri kushanda nemazvo.

Mafungiro Omutauro

Nezve mitauro yeHDL, vanhu vazhinji muChina vari kunetsana kuti ndeipi iri nani pakati peVHDL neVerilog. Muchokwadi, ini pachangu ndinofunga kuti izvi hazvina zvazvinoreva. Mazhinji makambani makuru kunze anoshandisa Verilog yeRTL-level kodhi, saka ini ndichiri kukurudzira munhu wese kuti adzidze Verilog zvakanyanya sezvinobvira. Panyaya yekuenzanisa, nekuti VHDL haina kusimba pane Verilog mukuita modhi, kune mashoma mashoma ekuenzanisa mamodheru akaitwa neVHDL. Ehe, Verilog haina kukwana futi. Muchokwadi, kugona kwaVerilog mukuomarara kwemaitiro ekuenzanisira zvakare kushoma. Semuenzaniso, haisati yatsigira arrays. Mune mamwe madhizaini akaomesesa egorigorithm, mitauro yepamusoro-soro inodiwa pakubvisa kutsanangura maitiro. Munyika dzekunze, mhando dzakawanda dzekuenzanisa dzinoitwa uchishandisa SystemC uye E mutauro, uye kushandisa Verilog kunoonekwa sechinyakare. Huawei's verification platform muChina inoita kunge yakanyorwa muSystemC.

Maonero Anouya

Panyaya yedhizaini yekuvaka, nekuti dhizaini yandiri kushanda haina kukura zvakakwana, ini handisati ndave neruzivo rwakawanda. Ini ndinongonzwa kuti ndinofanira kunge ndiine ruzivo rwekugadzira komputa system. Hwaro hwekutanga hwekukamura kuita, hunoteverwa nekusarudza yakakodzera bhazi chimiro, dhizaini chimiro, uye processor architecture. Iyo kupatsanurwa kwehurongwa hwekuvaka kunofanirwa kuita kuti yega yega inoshanda module yakajeka uye nyore kuita. Ndinofunga ndichagovera mamwe manzwisisiro mushure mekunge ndave nechiitiko chidiki muchikamu chino munguva pfupi, saka handisi kuzokurasisa iwe izvozvi.

Maonero Pamunhu

Pakupedzisira, regai ndipfupise muchidimbu. Izvo zvese zvinodzika kune kwakawanda kudzidzira, kufunga kwakawanda, uye kubvunza kwakawanda. Kudzidzira kunoita kuti zvive zvakakwana. Zviri nani kuzvidzidzira iwe pachako pane kuverenga mhinduro dzevamwe kazana. Kurudziro yekudzidzira inouya chikamu kubva mukufarira uye pamwe nekumanikidzwa. Ini pachangu ndinofunga kuti yekupedzisira inonyanya kukosha. Kuva nezvinodiwa zvinogadzira nyore kudzvanywa, ndiko kuti, zvakanakisa kudzidzira mukukudziridza kweprojekiti pane kudzidza nekuda kwekudzidza.

Mukuita maitiro, iwe unofanirwa kufunga zvakanyanya uye kufunga nezve zvikonzero zvezvinetso. Mushure mekugadzirisa matambudziko, bvunza kuti nei dzimwe nguva shoma. Iyi inzira zvakare yekuunganidza ruzivo. Kana uine tsika yekunyora matanda epurojekiti, zviri nani. Nyora pasi matambudziko, zvikonzero, mhinduro, uye nzira dzinogadziriswa mairi. Pakupedzisira, bvunza mibvunzo yakawanda. Kana iwe usingakwanise kugadzirisa dambudziko mushure mekufunga nezvazvo, bvunza. Mushure mezvose, hunyanzvi hwemunhu hushoma. Bvunza vaunodzidza navo, vaunoshanda navo, injini dzekutsvaga, uye netizens. Chinyorwa kana nhungamiro yeshamwari inogona kukubatsira kugadzirisa matambudziko nekukurumidza.

mhedziso

Mushure mekuita simulation, sezvo isu tiri kugadzira muFPGA, iyo RTL-level kodhi inovimbiswa kuenderana neiyo synthesis mhedzisiro uye inoshanda simulation mhedzisiro panguva yekugadzira. Chero bedzi iyo static timing report mushure meiyo synthesis dhizaini isina kunyeverwa pamusoro pekutyora zvimisikidzo zvenguva, tinogona kuenderera mberi nekugadzirisa pabhodhi. Muchokwadi, paHuawei neZTE, ivowo havaite yekufananidza nguva kana vachigadzira FPGA nekuti kutevedzera nguva kunotora nguva yakawanda uye mhedzisiro yacho haisati iri nani pane kutarisa static nguva yekuongorora rondedzero.

Ehezve, kana iri ASIC dhizaini, basa rekuita rekuenzanisira rakakura. Kana ichisanganisira akawanda-wachi domain dhizaini, post-simulation inowanzoitwa. Nekudaro, usati waita post-simulation, maturusi ekusimbisa echokwadi anowanzo shandiswa uye iyo static nguva yekuongorora rondedzero inoshandiswa kutarisa chero kutyorwa kwezvinodiwa dhizaini. Mushure mekuita izvi, basa rekuita post-simulation rinogona kunge ridiki.

Kana chinodiwa ichi chichikanganisa kuburitswa kwechinhu kana kuburitswa kwechinhu, chienzanise nekushandiswa kwechinhu chemagetsi uye kuenzanisa kugadzirwa kwechinhu usati watumira mafaira ekupedzisira kuti aongororwe.