PCB Decoupling Capacitor Placement Guide

Decoupling capacitor placement is not just about proximity to the IC — it is about minimizing the inductance of the current loop from capacitor to power pin. A capacitor placed 2 mm away with a poor via design can perform worse than one placed 5 mm away with optimized via geometry.

🕑 15 min read  |  Level: Advanced  |  Updated: May 2025  |  Part of: PCB Power Integrity Design Guide

Table of Contents

1. Why Placement Matters More Than Value Selection
2. Mounting Inductance: The Critical Parameter
3. Via Design for Decoupling Capacitors
4. Pad Geometry and Footprint Optimisation
5. Placement Rules by IC Package Type
6. Capacitor Value Selection and Effective Frequency
7. Common Placement Mistakes and Fixes
8. Frequently Asked Questions

This guide focuses on decoupling capacitor placement, via design, and pad geometry — the physical layout decisions that determine whether your decoupling strategy actually works. For the broader power integrity framework including PDN impedance targets and plane design, see the main PCB power integrity design guide.

1) Why Placement Matters More Than Value Selection

Most engineers spend significant time selecting decoupling capacitor values and far less time on placement — yet placement is the larger determinant of high-frequency effectiveness.

Every decoupling capacitor has a self-resonant frequency (SRF) determined by its capacitance and its total effective series inductance (ESL). Above the SRF, the capacitor becomes inductive and provides no decoupling benefit. The total ESL includes:

• Package ESL: Fixed by body size — 0201 ≈ 0.2–0.4 nH; 0402 ≈ 0.4–0.8 nH; 0603 ≈ 0.8–1.5 nH
• Pad and trace inductance: 0.5–2 nH depending on trace length between capacitor pads and vias
• Via inductance: 0.5–1 nH per via per mm of via length in the dielectric
• Plane spreading inductance: 0.1–0.5 nH from current spreading in the plane to the IC power pin

A 100 nF capacitor with an SRF of 50 MHz based on package ESL alone can have an effective SRF of only 20 MHz after adding 1 nH of via inductance. Proper placement that eliminates unnecessary trace inductance recovers this frequency range.

2) Mounting Inductance: The Critical Parameter

Mounting inductance (L_mount) is the total loop inductance of the current path from capacitor through vias to the power plane, through the plane to the IC power via, and back through the GND plane to the capacitor GND via.

Mounting Inductance vs Placement Scenario

Calculating Via Mounting Inductance

L_via ≈ 5.08 × h × [ln(4h/d) + 1] pH

Where h = via length through dielectric in inches and d = drill diameter in inches. Example: 1.6 mm board, 0.3 mm drill → L_via ≈ 1.1 nH per via.

3) Via Design for Decoupling Capacitors

Four via configurations are used in practice, ranked from worst to best performance:

Configuration 1 — Single Via, Remote Placement (Avoid)

One via each for PWR and GND placed at the end of a trace. Trace inductance adds to via inductance, pushing effective SRF below 20 MHz for most 100 nF capacitors. Acceptable only for low-frequency bulk capacitors.

Configuration 2 — Via Adjacent to Pad (Standard)

Vias placed immediately adjacent to each capacitor pad, minimal trace between pad and via. Trace inductance minimised to 0.1–0.3 nH. Minimum acceptable for capacitors operating above 50 MHz. Via centre-to-pad edge distance must not exceed 0.3 mm.

Configuration 3 — Dogbone Via (High Performance)

Two vias per capacitor, one per pad, placed as close to the pads as DRC allows, with PWR and GND vias on opposite sides of the capacitor body. Creates the shortest possible current loop. Effective up to 200–500 MHz with 0402 capacitors.

Configuration 4 — Via-in-Pad (Maximum Performance)

The via is placed directly within the capacitor pad. Eliminates all pad-to-via trace inductance. Requires filled, capped, and planarised vias. Adds approximately 15–25% to PCB fabrication cost. Standard for high-speed boards above 1 Gbps. See our via-in-pad design and manufacturing guide.

Multiple Vias in Parallel

Two vias in parallel reduce effective inductance to approximately 60% of a single via. Three vias in parallel: approximately 45%. For high-current decoupling capacitors (47 µF and above), use 2–4 vias per pad to reduce both inductance and thermal resistance.

4) Pad Geometry and Footprint Optimisation

For 0402 capacitors used above 100 MHz, reduce pad length from IPC standard 0.8 mm to 0.5–0.6 mm. This reduces effective trace inductance by 0.1–0.2 nH while maintaining adequate solderability. Verify any footprint modification with your assembly partner before production.

Increasing pad width from standard 0.5 mm to 0.7–0.8 mm for power decoupling capacitors reduces inductance by approximately 15–20% with no manufacturing penalty.

Minimise the clearance hole (anti-pad) in non-connecting planes to 0.1–0.15 mm beyond drill diameter. Oversised anti-pads reduce effective plane capacitance and slightly increase spreading inductance.

5) Placement Rules by IC Package Type

BGA Packages

BGA power balls are inside the component footprint. For 1.0 mm pitch and above: place 0201 capacitors directly under the BGA between balls. For all pitches: position first-row capacitors within 1–2 mm of the nearest power ball. For fine-pitch BGA at 0.65 mm and below: use via-in-pad on BGA escape vias combined with 0201 capacitors immediately outside the component boundary. See our BGA PCB assembly guide.

QFN Packages

QFN packages expose the power pad on the bottom centre. Place decoupling capacitors as close as possible to the power pad perimeter, with vias connecting to the internal power plane directly under the QFN thermal pad.

Through-Hole Power Connectors

Place bulk decoupling capacitors (47–470 µF) within 10 mm of the connector pins on the same layer. Place high-frequency decoupling (100 nF) between the bulk capacitors and the load path.

6) Capacitor Value Selection and Effective Frequency

SRF = 1 / (2π × √(C × L_total)) where L_total = package ESL + mounting inductance.

Use at least three different value decades per power rail to ensure continuous coverage. A single capacitor value, however close to the IC, leaves significant frequency gaps in the PDN impedance profile.

7) Common Placement Mistakes and Fixes

8) Frequently Asked Questions

Does the decoupling capacitor need to be on the same layer as the IC?

Yes, when possible. Opposite-side placement requires the current loop to traverse the full board thickness twice, approximately doubling effective via inductance. For double-sided assemblies where opposite-side placement is unavoidable, use via-in-pad to minimise the via inductance contribution.

How close does a decoupling capacitor need to be to the IC?

What matters is mounting inductance, not physical distance. A capacitor 5 mm away with via-in-pad and a 0201 package may provide better decoupling than a 0603 capacitor 1 mm away with a long trace to a remote via. For capacitors targeting above 100 MHz: keep via-to-pad distance under 0.5 mm and the capacitor within 3 mm of the IC power pin.

Can I use a single large capacitor instead of multiple smaller ones?

A single large capacitor provides good low-frequency decoupling but leaves the PDN unprotected above its SRF. Multiple capacitors in parallel — particularly different values — provide broader bandwidth. The parallel combination of 10 µF + 100 nF + 10 nF covers approximately 100 times more frequency bandwidth than any single capacitor alone.

What dielectric type should I use for decoupling capacitors?

Use X7R or X5R dielectric MLCCs for power decoupling. Avoid Y5V dielectric — its capacitance decreases 70–80% under DC bias, so a 10 µF Y5V cap may provide only 2–3 µF at operating voltage. C0G (NP0) has excellent stability but is only available in small values and is primarily used for RF filtering.

Should decoupling capacitors use thermal relief or direct connect to the power plane?

Always use direct connects. Thermal relief spokes add 0.5–2 nH of inductance due to narrow spoke geometry, significantly degrading high-frequency performance. Reserve thermal relief for components requiring hand soldering or in-circuit testing access.

For the complete power integrity framework — PDN impedance calculation, power plane design, and SSN control — see our PCB power integrity design guide. For via-in-pad fabrication requirements, contact Highleap Electronics.

Effective decoupling capacitor placement is critical for maintaining PDN performance and minimizing high-frequency voltage ripple. By carefully considering mounting inductance, via geometry, pad design, and proximity to IC power pins, engineers can optimize the effective self-resonant frequency and ensure continuous impedance coverage across the power rail. Implementing advanced strategies such as via-in-pad or multiple parallel vias further reduces loop inductance and enhances decoupling efficiency, supporting high-speed and high-density PCB designs. Proper execution of these principles is essential for reliable power integrity in modern multilayer boards.