Don’t let PCB vias ruin your entire board

Don’t let PCB vias ruin your entire board! Vias are an essential part of multi-layer PCBs, with drilling costs typically accounting for 30% to 40% of the PCB manufacturing cost. In simple terms, every hole on a PCB can be called a via.

PCB drilling classification

From a functional perspective, vias can be divided into two categories:

Electrical Connection Between Layers: Used to connect different layers of the PCB for electrical purposes.
Fixture or Positioning for Components: Used for fixing or positioning components.

From a process perspective, these vias are generally divided into three types:

Blind vias, buried vias, and through vias.

Blind Vias: Located on the top and bottom surfaces of the PCB, these vias have a certain depth and are used to connect surface traces to inner layer traces. The depth of the hole usually does not exceed a certain ratio (diameter).
Buried Vias: These are vias located within the inner layers of the PCB, not extending to the surface of the board. Both of these types of vias are located within the inner layers of the PCB and are formed before lamination using through-hole forming processes, which may overlap several inner layers during via formation.
Through Vias: These vias pass through the entire PCB and can be used for internal interconnection or as mounting holes for components.

Due to their easier implementation in the manufacturing process and lower cost, the vast majority of printed circuit boards use through vias rather than the other two types of vias. Unless otherwise specified, the vias mentioned below are considered through vias.

From a design perspective, a via mainly consists of two parts:

• Via Components and Design Considerations: A via in PCB design comprises a central drill hole surrounded by a pad area, where the dimensions of these parts determine the overall via size. In high-speed and high-density PCB designs, minimizing via size is crucial to optimize routing space and reduce parasitic capacitance, enhancing suitability for high-speed circuits.

• Cost and Size Limitations: However, shrinking via size increases manufacturing costs due to longer drilling times and potential deviations in positioning during processes like drilling and plating. When the depth of the hole exceeds six times its diameter, ensuring uniform copper plating along the hole wall becomes challenging, impacting both cost and manufacturability.

• Technological Advancements and Microvias: Recent advancements in laser drilling technology have enabled the use of smaller vias. Vias with diameters of 6 mils or less are termed microvias and are commonly employed in HDI designs. These microvias support via-in-pad configurations, significantly improving circuit performance and conserving routing space on the PCB.

• Signal Integrity Concerns: Vias introduce impedance discontinuities in transmission lines, which can lead to signal reflections. The impedance of a via is approximately 12% lower than that of the transmission line, causing a slight reduction in impedance. Despite this, the actual reflection coefficient is minimal, typically around 0.06, due to well-managed design practices and manufacturing techniques.

• Parasitic Capacitance and Inductance: The primary challenges associated with vias in PCB design relate to managing parasitic effects such as capacitance and inductance. These factors are critical in high-frequency designs where maintaining signal quality and minimizing transmission losses are paramount.

 Parasitic Capacitance and Inductance of Vias

Parasitic Capacitance of Vias

Vias themselves have parasitic capacitance to ground. If the isolation hole diameter of the via on the ground layer is known to be D2, and the pad diameter of the via is D1, with a PCB thickness of T and a substrate dielectric constant of ε, the parasitic capacitance of the via is approximately:

C=1.41εTD1/(D2−D1)

The parasitic capacitance of the via will mainly affect the rise time of the signal, reducing the circuit’s speed. For example, for a PCB with a thickness of 50 mils, if a via with an inner diameter of 10 mils and a pad diameter of 20 mils is used, and the distance between the pad and the ground copper area is 32 mils, the parasitic capacitance of the via can be approximately calculated as:

C=1.41×4.4×0.050×0.020/(0.032−0.020)=0.517pF

The change in rise time caused by this capacitance is:

T10−90​=2.2C(Z0​/2)=2.2×0.517×(55/2)=31.28ps

Although the effect of the capacitance of a single via on the rise time is not very obvious, if vias are used multiple times in the routing for interlayer switching, designers should still consider it carefully.

Parasitic Inductance of Vias

Parasitic Inductance of Vias Similarly, while vias have parasitic capacitance, they also have parasitic inductance. In the design of high-speed digital circuits, the harm caused by the parasitic inductance of vias is often greater than that of the parasitic capacitance. Its parasitic series inductance weakens the contribution of bypass capacitance and weakens the filtering effect of the entire power supply system.

We can use the following formula to calculate the approximate parasitic inductance of a via:

L=5.08h[ln(4h/d)+1]

Where L is the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole. From the formula, it can be seen that the diameter of the via has a relatively small impact on the inductance, while the length of the via affects the inductance. Using the example above, we can calculate the inductance of the via as follows:

L=5.08×0.050[ln(4×0.050/0.010)+1]=1.015nH

If the rise time of the signal is 1 ns, then its equivalent impedance is:

XL=πL/T10−90​=3.19Ω

Such an impedance cannot be ignored when there is high-frequency current passing through. In particular, when connecting the bypass capacitor to the power and ground layers, it needs to pass through two vias, which doubles the parasitic inductance of the via.

Via Design in High-Speed PCBs

Through the analysis of the parasitic characteristics of vias above, it can be seen that in high-speed PCB design, seemingly simple vias can often bring significant negative effects to the circuit design.

To reduce the adverse effects of the parasitic effects of vias, the following content can be arranged in the design as much as possible:

Choose vias of reasonable size considering both cost and signal quality. For example, for the PCB design of 6-10 layer memory modules, it is better to use vias with a diameter of 10/20 mils (drill hole/pad). For some high-density small boards, you can also try using 8/18 mils vias. Under current technological conditions, it is difficult to use smaller vias. For power or ground vias, consider using larger sizes to reduce impedance.

As discussed above, using a thinner PCB is beneficial to reduce the two parasitic parameters of vias.
Power and ground pins should be placed as close as possible to the vias, and the leads between the vias and the pins should be as short as possible, as they will increase the inductance. At the same time, the leads of the power and ground should be as thick as possible to reduce impedance.

Try to minimize the use of vias for signal routing on the PCB, that is, try to reduce unnecessary vias.
Place some grounding vias near the vias where the signal changes layers to provide a nearby return path for the signal. You can even place a large number of redundant grounding vias on the PCB. Of course, flexibility and changeability are also needed in the design.

The above discussion of the via model assumes that each layer has pads. Sometimes, we can reduce or even eliminate the pads on some layers. Especially when the density of vias is very high, it may cause a slot to form a barrier loop in the copper layer. In addition to moving the position of the via, we can also consider reducing the size of the pad of the via on the copper layer.

Conclusion

PCB vias are crucial components in multi-layer PCBs, accounting for a significant portion of manufacturing costs. Vias are categorized based on their function as either providing electrical connections between layers or serving as fixtures for components. From a process perspective, vias are classified into blind, buried, and through vias. While blind and buried vias are located within the inner layers of the PCB, through vias pass through the entire board.

Designers aim for smaller vias in high-speed and high-density PCBs to maximize routing space and reduce parasitic capacitance. However, there are limits to size reduction due to manufacturing constraints such as drilling and plating. The development of laser drilling technology has enabled the use of microvias, enhancing circuit performance and saving space.

Despite their benefits, vias can introduce impedance discontinuities on transmission lines, causing minimal signal reflection. The main issues with vias are related to parasitic capacitance and inductance, which can affect signal speed and filtering in high-speed digital circuits. To mitigate these effects, designers should carefully consider via size, placement, and routing strategies in high-speed PCB designs.