PCB Power Distribution Network Design

The power distribution network (PDN) is the infrastructure that delivers stable voltage to every IC on your board. Designing a PDN that maintains target impedance from DC to several hundred MHz requires a systematic approach to VRM selection, capacitor sizing, and plane geometry — none of which can be done by intuition alone.

Table of Contents

1. PDN Architecture and Frequency Regions
2. Target Impedance Calculation
3. VRM Selection and Bulk Capacitor Sizing
4. Plane Capacitance and PDN Simulation
5. PDN Measurement, Validation and FAQ

This guide covers the complete PCB power distribution network design process — from defining impedance targets through VRM selection, capacitor sizing, simulation, and post-fabrication validation. For the broader power integrity framework including decoupling placement and plane design, see the main PCB power integrity design guide.

1. PDN Architecture and Frequency Regions

A complete PDN spans multiple physical domains, each contributing inductance, resistance, and capacitance to the overall impedance. The critical insight is that no single component or design element controls impedance across the full frequency range. Each domain has a characteristic frequency range where it dominates, and each requires independent design attention.

The PDN bandwidth requirement is set by the fastest current transient the load can produce:

f_max = 0.5 / t_rise
For a processor with 1 ns current rise time: f_max = 500 MHz.
For DDR5 at 6400 MT/s with 100 ps edge rates: f_max extends to 5 GHz, requiring careful package and die capacitance management.

The design goal is to maintain Z < Z_target continuously from DC through f_max. Any frequency gap where PDN impedance exceeds Z_target is a potential source of voltage droop, oscillation, or logic failure at the corresponding switching frequency.

2. Target Impedance Calculation

Target impedance is the single most important PDN design specification. It converts the voltage ripple tolerance into a quantitative impedance budget that every component selection and layout decision must satisfy.

Z_target = (V_supply × ripple%) / I_peak
V_supply: nominal supply voltage  |  ripple%: maximum allowed ripple fraction  |  I_peak: peak instantaneous current from IC datasheet

These numbers illustrate the extreme range of PDN requirements. A GPU core rail at 0.1 mΩ demands a near-perfect PDN — every milliohm of parasitic inductance in the PCB stackup, VRM output impedance, or via array has measurable impact. Getting these targets right before starting layout prevents costly respins.

I_peak appears in the IC datasheet as maximum supply current, peak operating current, or as transient current waveforms in the application section. For FPGAs and processors, vendor power estimation tools (Xilinx Power Estimator, Intel VID) provide more accurate values than datasheet maximums. If no value is available, measure VRM output current with a current probe on a working system and add 20–30% margin for worst-case operation.

3. VRM Selection and Bulk Capacitor Sizing

The VRM dominates PDN impedance from DC to its feedback loop bandwidth. Below loop bandwidth, the VRM actively regulates output, presenting milliohm-range impedance. At the crossover frequency, impedance peaks — this is the most critical transition to manage. Above loop bandwidth, VRM output impedance rises and bulk capacitors take over.

High-current rails above 20–30 A require multiphase VRM configurations. Multiple phases interleave their switching cycles, reducing output current ripple by a factor equal to the number of phases, allowing smaller output inductors, and distributing thermal load across multiple power devices. For AI accelerator PCBs requiring 200+ A supplies, 8–16 phase VRM designs are standard.

Bulk Capacitor Sizing

Bulk capacitors bridge the impedance gap between VRM loop bandwidth and the frequency range where ceramic decoupling takes over. The minimum bulk capacitance to prevent the impedance from rising above Z_target at the VRM crossover is:

C_bulk = 1 / (2π × f_crossover × Z_target)
Example: Z_target = 5 mΩ, f_crossover = 200 kHz → C_bulk = 159 µF minimum

For high-speed digital designs, large MLCC arrays are preferred due to their combination of low ESR, low ESL, and stable capacitance versus frequency and temperature. A parallel array of multiple MLCC values — for example, one 100 µF in parallel with several 10 µF — provides broader effective decoupling bandwidth than a single large capacitor type of either value alone.

4. Plane Capacitance and PDN Simulation

PCB copper planes exhibit distributed capacitance between adjacent power and ground planes. This plane capacitance is effective above 100 MHz — exactly where discrete capacitors have become inductive and no longer contribute to PDN decoupling.

C_plane = ε₀ × ε_r × A / d
ε₀ = 8.854 × 10⁻¹² F/m  |  ε_r = 4.3 (FR-4)  |  A = overlapping plane area (m²)  |  d = dielectric thickness (m)
Example: 100×100 mm board, 4 mil FR-4 between GND and PWR planes → C_plane ≈ 3.8 nF

While 3.8 nF is small in absolute terms, it is distributed uniformly across the entire board area and presents very low inductance at high frequencies. To maximise plane capacitance: use 3–4 mil prepreg between GND and PWR planes (not 10+ mil core); maximise overlapping copper area and avoid unnecessary plane cutouts; and consider high-ε_r embedded capacitance materials (such as Sanmina C-Ply) for boards with Z_target below 5 mΩ above 100 MHz — these materials can increase plane capacitance by 100× over standard FR-4.

PDN Simulation Methods

PDN simulation validates that the designed network achieves target impedance before fabrication. Three approaches are used in practice, in increasing order of accuracy:

• Spreadsheet-based lumped model: Models PDN segments as series R-L-C networks. Fast and identifies major design issues, but misses plane resonances and spatial effects. Best for initial VRM selection and bulk capacitor count estimation.
• S-parameter PDN simulation (Ansys SIwave, Cadence Sigrity, HyperLynx PI): Full EM simulation of PCB planes. Captures plane resonance peaks, anti-resonance nulls, effect of plane splits, and capacitor placement optimisation. Required when Z_target is below 10 mΩ.
• Time-domain simulation: Uses realistic IC current profiles from IBIS power models or measured waveforms. Provides direct voltage droop predictions under actual switching conditions. Most accurate method for worst-case sign-off analysis.

5. PDN Measurement, Validation and FAQ

After PCB fabrication, verify PDN impedance before full system assembly to confirm that simulation results are achieved in hardware. Discrepancies between simulation and measurement most commonly arise from inaccurate component models, unmodelled parasitic inductance in vias or connectors, or plane resonances shifted by actual dielectric properties.

1-Port VNA Measurement

Measure S11 at the IC power pin location with VRM and decoupling capacitors populated, IC removed. S11 converts to impedance:

Z = Z₀ × (1 + S11) / (1 − S11)
Z₀ = 50 Ω (VNA port impedance). For Z < 100 mΩ, use 2-port shunt-through measurement for improved accuracy at low impedance values.

Time-Domain Validation

With the system fully assembled, use a power rail probe (20 MHz bandwidth minimum, 1 GHz preferred) at the IC power pin under full operating load. Verify: peak-to-peak voltage ripple is within the allowed ripple budget; no transient droop exceeds the minimum operating voltage specification; and switching regulator ripple frequency is visible and within expected amplitude.

Frequently Asked Questions

What causes an anti-resonance peak in PDN impedance?

An anti-resonance peak occurs where the impedance of one capacitor type (becoming inductive above its SRF) intersects the impedance of the next capacitor type (still capacitive). Impedances add instead of cancel at this intersection, creating a peak that can exceed Z_target. Suppress it by using capacitors with slightly different values to spread the resonance frequency, adding resistive damping capacitors in parallel, or choosing capacitor types with higher ESR at the crossover frequency.

Can I use ferrite beads to isolate PDN sections?

Ferrite beads are appropriate for isolating sensitive analog or RF rails from digital switching noise above 10–100 MHz. Do not use ferrite beads in series with high-current digital supply paths — their impedance causes significant voltage drop under load, and non-linear behaviour can cause VRM instability.

How many VRM phases do I need?

A general guideline is 10–15 A per phase for standard integrated FET VRM designs. For a 60 A CPU rail, use 4–6 phases. For GPU or AI accelerator rails at 200 A+, 12–16 phases are typical. More phases reduce output ripple, allow smaller inductors, and improve transient response bandwidth at the cost of greater controller and FET count.

For related power integrity topics, see our guides on decoupling capacitor placement, power plane design techniques, simultaneous switching noise reduction, and multilayer PCB stackup design. Highleap Electronics provides PDN design review and high-speed PCB fabrication. Request a quote for your project.