ITEQ IT-988GSE PCB for Ultra-Low-Loss 100G and 400G Backplanes

An IT-988GSE PCB should be selected from the channel loss budget, not from the product label “100G” or “400G.” Aggregate system throughput does not reveal the lane rate, encoding method, Nyquist frequency, routing length, connector count, via topology, or allowable insertion loss. Two boards marketed for the same Ethernet generation can require very different laminate performance.

ITEQ positions IT-988GSE as an ultra-low-loss, high-Tg, halogen-free laminate and prepreg family for channels beyond 56 Gbps per lane. Its published 10 GHz dissipation factor is approximately 0.0014, but that number is only one part of the channel. Copper roughness, glass weave, finished copper thickness, via stubs, return-path discontinuities, connectors, packages, and manufacturing variation can consume as much or more margin than the dielectric itself.

The correct engineering question is therefore: after every avoidable discontinuity and conductor-loss source has been reduced, does the remaining channel still need the lower dielectric loss of IT-988GSE? This article treats the material as part of a quantified interconnect system rather than as a premium brand substitution.

Why IT-988GSE Is Chosen for Ultra-Low-Loss Channels

At high lane rates, the PCB behaves as a distributed transmission network. Dielectric polarization loss increases with frequency, conductor current crowds toward the copper surface, glass-weave variation changes local delay, and every via or connector introduces return loss and mode conversion. A material such as IT-988GSE is valuable when dielectric loss is a meaningful part of the total attenuation and the route length is long enough for that difference to matter.

ITEQ’s public material information identifies IT-988G and IT-988GSE as products intended for channel data rates beyond 56 Gbps. Its current product overview places IT-988GSE in the ultra-low-loss tier and publishes a typical Dk of about 3.21 and Df of 0.0014 for the stated comparison condition. Older detailed product data also show why the exact resin content and test method must accompany every dielectric value.

For the broader selection process, compare IT-988GSE with other ultra-low-loss high-speed materials using the same frequency, resin content, copper profile, and test method.

The material is justified by reach and margin

IT-988GSE is most likely to be justified in long backplanes, high-layer-count switch cards, chassis interconnects, data-center infrastructure, storage systems, and other channels where the board contributes a substantial portion of the total loss. It may be unnecessary for a short chip-to-chip route, a small daughtercard, or a design with enough equalization and margin to use a less expensive material.

A useful pre-layout decision includes:

• lane rate and modulation format;
• maximum routed length by layer;
• connector and package models;
• target insertion-loss mask at Nyquist and harmonic frequencies;
• via count and residual stub allowance;
• crosstalk and mode-conversion limits;
• available transmitter equalization and receiver margin;
• expected process and temperature variation.

Low Df does not repair bad topology

An ultra-low-loss dielectric cannot compensate for an unterminated via stub, a poorly designed connector launch, a split reference plane, excessive antipad capacitance, or uncontrolled return-via placement. Before upgrading the material, optimize the topology. Otherwise the design pays for lower dielectric loss while leaving larger discontinuities untouched.

Material Snapshot for Release

The following values are typical manufacturer data and should not be treated as finished-board guarantees. The field-solver model must use the design Dk and Df for the exact core or prepreg construction, resin content, glass style, copper foil, and frequency.

Use construction-specific dielectric data

The effective Dk of a woven-glass composite depends on the resin fraction, glass style, pressed thickness, copper treatment, and test method. A thin high-resin prepreg layer can have a different effective Dk from a thick core even when both use IT-988GSE chemistry. The stackup should therefore list a Dk for each dielectric construction or a controlled modeling method supplied by the fabricator.

A practical release package separates three concepts:

1. datasheet Dk/Df, used to compare material families;
2. design Dk/Df, used in the field solver for the selected construction;
3. production evidence, such as TDR and insertion-loss coupons, used to confirm the manufactured result.

Loss Budget and Copper Roughness

The total attenuation of a high-speed channel includes dielectric loss, conductor loss, radiation, leakage, and discontinuity loss. In a well-contained stripline, dielectric and conductor loss dominate the distributed portion. IT-988GSE reduces dielectric loss, but conductor roughness can erase part of that advantage.

Copper profile is an electrical parameter

At high frequency, current flows close to the copper surface. A rough bonding surface increases the effective path length and changes the local electromagnetic field. The result is higher conductor loss and, in some models, a shift in effective impedance and phase delay. “One-ounce copper” is therefore not a sufficient specification. The fabrication package should identify the foil type or maximum roughness category, especially on critical high-speed layers.

Very-low-profile or reverse-treated copper can reduce loss, but the tradeoff includes peel strength, handling, inner-layer treatment, and process availability. The selected foil must be qualified with the laminate and the intended surface preparation.

Build the loss budget from measurable parts

A defensible loss budget includes:

• package breakout and BGA escape;
• routed trace attenuation by layer and length;
• connector insertion loss and return loss;
• via transition loss, including residual stubs;
• AC-coupling capacitor and pad discontinuities;
• reference-plane transitions and return-via structures;
• manufacturing tolerance for dielectric thickness and trace geometry;
• temperature and humidity effects where applicable;
• crosstalk and mode-conversion penalties.

The budget should identify which elements are simulated, which are supplied by component vendors, and which will be validated with coupons. A generic “maximum dB per inch” value is not enough for a channel that includes multiple launches and connectors.

Impedance is necessary but not sufficient

A trace can measure 100 ohms differential and still have excessive insertion loss, skew, or mode conversion. TDR confirms the local impedance profile; it does not fully characterize frequency-dependent attenuation. The manufacturing plan should combine TDR with S-parameter or insertion-loss evidence when the margin is tight. Highleap’s explanation of how impedance is controlled in high-speed boards covers the dimensional variables behind the nominal impedance target.

100G/400G Backplane Routing Rules

Backplane channels are difficult because they combine long traces, multiple connectors, thick boards, large via transitions, and tight crosstalk limits. The material decision should be frozen early enough to influence connector selection, layer assignment, backdrill strategy, and overall chassis architecture.

Choose layers by loss and manufacturability

Critical pairs should be placed on layers with controlled dielectric thickness, low-profile copper, continuous reference planes, and enough spacing to meet crosstalk limits. Very thin dielectrics can reduce trace width but may increase copper-roughness sensitivity and manufacturing tolerance. Very thick dielectrics can require wider traces and larger antipads. The stackup should balance loss, routing density, impedance, skew, and drilling constraints.

Minimize via-stub and launch penalties

A backplane via may extend through a thick board even when the signal uses only part of the barrel. The unused section behaves as a resonant stub. Backdrilling can remove most of that stub, but the residual depth, drill-to-copper clearance, registration, and inspection method must be specified. Blind or buried structures may provide a better electrical result in some architectures but increase cost and process complexity.

Connector launches should be modeled with the actual pad, antipad, barrel, backdrill, reference planes, and nearby return vias. A launch copied from a different stackup can become inductive or capacitive when dielectric thickness and copper dimensions change.

Control skew and glass-weave effects

Differential pairs routed over different glass and resin regions can develop intra-pair skew. Mitigation options include spread-glass constructions, routing at an angle to the weave, wider geometry, pair placement rules, and construction-specific simulation. The correct method depends on the lane rate, pair length, and selected glass style.

Preserve the return path

Every layer transition requires a controlled return-current path. Ground stitching vias should be close enough to the signal transition to prevent a large loop area. Avoid crossing plane splits or voids. When a pair changes its reference plane from ground to power, provide a deliberate AC return path and model the transition.

Fabrication and Lamination Controls

IT-988GSE is intended to fit advanced multilayer processing, but the lower-loss resin system, low-profile copper, high layer count, and tight impedance targets require a controlled manufacturing route. The fabricator should release the stackup before CAM so trace compensation and impedance tuning can be agreed without changing the electrical architecture.

Stackup and lamination controls

The traveler should control:

• exact IT-988GSE core and prepreg constructions;
• glass style, resin content, and target pressed thickness;
• copper foil type and inner-layer surface treatment;
• copper balance and resin-fill review;
• press-cycle parameters and thickness compensation;
• registration targets for high-layer-count builds;
• finished board thickness, bow, and twist;
• traceability to laminate, prepreg, and copper lots.

Large backplanes may require sequential lamination or special registration methods. The process plan must account for cumulative dimensional movement and the effect of copper distribution on panel flatness.

Drilling, desmear, plating, and backdrill

High aspect-ratio through holes and deep backdrills require stable drill quality, controlled smear removal, and uniform copper plating. Low-profile copper and specialty resin systems should not be exposed to an assumed FR-4 desmear recipe without qualification. The fabricator should verify hole-wall condition, glass-fiber protrusion, resin recession, and copper adhesion.

Backdrill depth should be measured, not inferred only from machine settings. Cross-sections or nondestructive verification can confirm residual stub length and breakout safety. Coupon location should represent the production panel and stackup.

Production validation

Depending on the channel margin, useful evidence includes:

• impedance coupons and TDR reports;
• insertion-loss coupons or differential S-parameters;
• backdrill residual-stub measurements;
• microsections through critical vias;
• final copper-thickness verification;
• lot traceability and certificate of conformance;
• CAF or thermal-stress testing for high-reliability programs.

A first-article board should be compared with the simulation model so the design Dk, roughness model, and manufacturing assumptions can be updated before volume production.

IT-988GSE vs IT-968G

IT-988GSE and IT-968G are both high-speed ITEQ materials, but they occupy different loss and cost positions. ITEQ’s current overview lists IT-988GSE at about Df 0.0014 and IT-968G at about Df 0.0039 for the stated comparison conditions. The difference is significant on a long route, but it does not automatically justify the higher-tier material on every board.

Compare identical channel constructions

The comparison should use the same trace geometry, copper roughness, layer transition count, connector models, via design, and test method. Comparing only two datasheet Df values can overstate or understate the real system difference. A short coupon can also hide connector and launch penalties that dominate the full backplane.

RFQ and FAQ

The RFQ should include protocol, lane rate, modulation, maximum route length, insertion-loss and return-loss masks, stackup, layer count, board size, finished thickness, copper profile, target impedance, connector details, via and backdrill structure, glass-weave strategy, surface finish, reflow exposure, coupon plan, and annual volume. Ask the fabricator to identify the exact IT-988GSE cores and prepregs and the design Dk/Df used for every dielectric layer.

Does IT-988GSE automatically support every 400G or 800G system?

No. Aggregate bandwidth does not define the channel. A design must be validated from lane rate, reach, modulation, topology, loss mask, and equalization capability.

Which Dk should be entered in the field solver?

Use construction-specific design Dk for the selected glass style, resin content, pressed thickness, frequency, and copper treatment. Do not use a family-level marketing number for every layer.

Is VLP copper mandatory?

Not universally, but low-profile copper is often necessary to preserve the benefit of the ultra-low-Df resin. The required profile should be determined from the conductor-loss model and qualified for adhesion.

Can IT-988GSE be mixed with lower-cost material?

Hybrid constructions are possible, but cure compatibility, resin flow, CTE, thickness movement, interface adhesion, and warpage must be validated. Keep critical channels on the intended low-loss layers.

What test best proves the channel is correct?

A combination is strongest: TDR for impedance and discontinuities, plus insertion-loss or S-parameter coupons for frequency-dependent performance. Functional system testing remains necessary.

Manufacturer references

• ITEQ launch announcement for IT-988G/IT-988GSE
• ITEQ product overview and comparative Dk/Df data